SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments (TI)
Widebus
Family
D
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
D
Translate Between GTLP Signal Levels and
LVTTL Logic Levels
D
Support Mixed-Mode (3.3 V and 5 V) Signal
Operation on A-Port and Control Inputs
D
B-Port Transition Time Optimized for
Distributed Backplane Loads
D
I
off
Supports Partial-Power-Down Mode
Operation
D
Bus Hold on A-Port Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
Package Options Include Plastic Shrink
Small-Outline (DL), and Thin Shrink
Small-Outline (DGG) Packages
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR.
description
The SN74GTLPH16612 is a medium-drive, 18-bit UBT (universal bus transceiver) that provides
LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, or
clock-enabled modes of data transfer. This device provides a high-speed interface between cards operating at
LVTTL logic levels and backplanes operating at GTLP signal levels. High-speed (about two times faster than
standard L VTTL or TTL) backplane operation is a direct result of the reduced output swing (<1 V), reduced input
threshold levels, and OEC (output edge control). These improvements minimize bus settling time and have
been designed and tested using several backplane models.
Drvr
V
TT
Conn.
.25”
.875”
.625” .625”
1” 1”
Slot 1 Slot 2
V
TT
.625”.625”
1”1”
Slot 16
Slot 8
.25”
R
TT
Conn. Conn. Conn.
Rcvr
Rcvr
Rcvr
R
TT
Volts – V
t – Time – ns
10 30
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
020
TI GTLPH16612
Fairchild GTLP16612
TI GTL16612
Figure 1. Test Backplane Model With Output Waveform Results
Copyright 2000, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI, OEC, UBT, and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Figure 1 shows actual device output waveforms using a synchronous clock at 75 MHz. The test backplane is
a 16-slot, 14-inch board with loaded impedance of 33 Ω. VTT is 1.5 V , V
REF
is 1 V , and RTT pullup resistor is 50 Ω.
The driver is in slot 8, with receivers in alternate slots 1, 3, 5, 7, 10, 12, 14, and 16. Receiver slot 1 signals are
shown. The signal becomes progressively worse as the receiver moves closer to the driver or the spacing
between receiver cards is reduced. The clock is independent of the data and the system clock frequency is
limited by the backplane flight time to about 80 MHz to 90 MHz. This frequency can be increased even more
(30% to 40%) if the clock is generated and transmitted together with the data from the driver card (source
synchronous).
The SN74GTLPH16612 is a medium-drive (34 mA), 18-bit universal bus transceiver, containing D-type latches
and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes. This UBT
can replace any of the functions shown in Table 1.
Table 1. SN74GTLPH16612 UBT Replacement Functions
FUNCTION 8 BIT 9 BIT 10 BIT 16 BIT 18 BIT
Transceiver ’245, ’623, ’645 ’863 ’861 ’16245, ’16623 ’16863
Buffer/driver ’241, ’244, ’541 ’827 ’16241, ’16244, ’16541 ’16825
Latched transceiver ’543 ’16543 ’16472
Latch ’373, ’573 ’843 ’841 ’16373 ’16843
Registered transceiver ’646, ’652 ’16646, ’16652 ’16474
Flip-flop ’374, ’574 ’821 ’16374
Standard UBT ’16500, ’16501
Universal bus driver ’16835
Registered transceiver with CLK enable ’2952 ’16470, ’16952
Flip-flop with CLK enable ’377 ’823 ’16823
Standard UBT with CLK enable ’16600, ’16601
SN74GTLPH16612 UBT replaces all above functions
GTLP is a TI derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The ac specification
of the SN74GTLPH16612 is given only at the preferred higher noise-margin GTLP , but this device can be used
at either GTL (VTT = 1.2 V and V
REF
= 0.8 V) or GTLP (V
TT
= 1.5 V and V
REF
= 1 V) signal levels.
The B port normally operates at GTLP levels, while the A-port and control inputs are compatible with LVTTL
logic levels and are 5-V tolerant. V
REF
is the reference input voltage for the B port.
To improve signal integrity, the SN74GTLPH16612 B-port output transition time is optimized for distributed
backplane loads.
VCC (5 V) supplies the internal and GTLP circuitry, while VCC (3.3 V) supplies the LVTTL output buffers.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven L VTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74GTLPH16612 is characterized for operation from –40°C to 85°C.
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEAB
LEAB
A1
GND
A2
A3
V
CC
(3.3 V)
A4
A5
A6
GND
A7
A8
A9
A10
A1 1
A12
GND
A13
A14
A15
V
CC
(3.3 V)
A16
A17
GND
A18
OEBA
LEBA
CEAB
CLKAB
B1
GND
B2
B3
V
CC
(5 V)
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
REF
B16
B17
GND
B18
CLKBA
CEBA
DGG OR DL PACKAGE
(TOP VIEW)
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional description
Data flow in each direction is controlled by the clock-enables (CEAB and CEBA), latch-enables (LEAB and
LEBA), clock (CLKAB and CLKBA), and output-enables (OEAB and OEBA).
For A-to-B data flow, when CEAB is low, the device operates on the low-to-high transition of CLKAB for the
flip-flop and on the high-to-low transition of LEAB for the latch path, i.e., if CEAB and LEAB are low, the A data
is latched, regardless of the state of CLKAB (high or low) and if LEAB is high, the device is in transparent mode.
When OEAB
is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state.
The data flow for B to A is similar to A to B, except that CEBA
, OEBA, LEBA, and CLKBA are used.
FUNCTION TABLE
†
INPUTS
OUTPUT
CEAB OEAB LEAB CLKAB A
B
MODE
X H X X X Z Isolation
L L L H or L X B
0
‡
L L L H or L X B
0
§
Latched storage of A data
X L H X L L
p
X LH XH H
Transparent
L L L ↑ L L
L LL ↑ HH
Clocked storage of A data
H L L X X B
0
§
Clock inhibit
†
A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA,
and CEBA
.
‡
Output level before the indicated steady-state input conditions were established, provided
that CLKAB was high before LEAB went low.
§
Output level before the indicated steady-state input conditions were established.
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
CLK
1D
C1
CLK
B1
OEAB
CEAB
CLKAB
LEAB
LEBA
CLKBA
CEBA
OEBA
A1
To 17 Other Channels
CE
CE
1
56
55
2
28
30
29
27
3
54
V
REF
35
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC: 3.3 V –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 V –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1): A-port and control inputs –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
B port and V
REF
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, V
O
(see Note 1): A port –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
O
: A port 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port 80 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any A-port output in the high state, I
O
(see Note 2) 64 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DGG package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 56°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Notes 4 through 6)
MIN NOM MAX UNIT
pp
3.3 V 3.15 3.3 3.45
VCCSuppl
y v
oltage
5 V 4.75 5 5.25
V
GTL 1.14 1.2 1.26
VTTTermination voltage
GTLP 1.35 1.5 1.65
V
pp
GTL 0.74 0.8 0.87
V
REF
Suppl
y v
oltage
GTLP 0.87 1 1.1
V
p
B port V
TT
VIInput voltage
Except B port 5.5
V
p
B port V
REF
+50 mV
VIHHigh-level input voltage
Except B port 2
V
p
B port V
REF
–50 mV
VILLow-level input voltage
Except B port 0.8
V
I
IK
Input clamp current –18 mA
I
OH
High-level output current A port –32 mA
p
A port 64
IOLLow-level output current
B port 34
mA
T
A
Operating free-air temperature –40 85 °C
NOTES: 4. All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application
report
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
5. Normal connection sequence is GND first, VCC = 5 V second, and VCC = 3.3 V , I/O, control inputs, VTT, and V
REF
(any order) last.
6. VTT and RTT can be adjusted to accommodate backplane impedances as long as they do not exceed the dc absolute IOL ratings.
Similarly, V
REF
can be adjusted to optimize noise margins, but normally is 2/3 VTT.
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V, II = –18 mA –1.2 V
VCC (3.3 V) = 3.15 V to 3.45 V,
VCC (5 V) = 4.75 V to 5.25 V
IOH = –100 µA
VCC (3.3 V)
–0.2
V
OH
A port
IOH = –8 mA 2.4
V
V
CC
(3.
3V)
= 3.15 V,
V
CC
(5 V) = 4.75
V
IOH = –32 mA 2
IOL = 100 µA 0.2
p
IOL = 16 mA 0.4
V
OL
A port
V
CC
(3.3V)
= 3.15 V,
V
CC
(5 V)
= 4.75
V
IOL = 32 mA 0.5
V
IOL = 64 mA 0.55
B port VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V, IOL = 34 mA 0.65
Control
inputs
VCC (3.3 V) = 0 or 3.45 V, VCC (5 V) = 0 or 5.25 V, VI = 5.5 V 10
VI = 5.5 V 20
I
A port
VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V
VI = VCC (3.3 V)
1
µ
A
I
VI = 0 –30
µ
p
VI = VCC (3.3 V) 5
B port
V
CC
(3.
3V)
= 3.45 V,
V
CC
(5 V) = 5.25
V
VI = 0 –5
I
off
VCC = 0, VI or VO = 0 to 4.5 V 100 µA
VI = 0.8 V 75
I
I(hold)
A port VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V
VI = 2 V
–75
µA
()
VI = 0 to VCC(3.3 V)
‡
±500
A port VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = VCC (3.3 V) 1
I
OZH
B port VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 1.5 V 10
µ
A
A port VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 0 –1
I
OZL
B port VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 0.65 V –10
µ
A
Outputs high 1
I
CC
A or BpVCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, IO = 0,
§
¶
Outputs low 5
mA
(3.3V)
ort
V
I
=
V
CC
(3.3 V) or
GND
§
,
V
I
=
V
TT
or
GND
¶
Outputs disabled 1
Outputs high 120
I
CC
A or BpVCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, IO = 0,
§
¶
Outputs low 120
mA
(5 V)
ort
V
I
=
V
CC
(3.3 V) or
GND
§
,
V
I
=
V
TT
or
GND
¶
Outputs disabled 120
∆ICC (3.3 V)
#
VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V , One A-port or control input at 2.7 V,
Other A-port or control inputs at VCC (3.3 V) or GND
1 mA
C
i
Control
inputs
VI = 3.15 V or 0 4 pF
A port VO = 3.15 V or 0 8.5
p
C
io
B port VO = 1.5 V or 0 8
pF
†
All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C.
‡
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§
This is the VI for A-port or control inputs.
¶
This is the VI for B port.
#
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, V
TT
= 1.5 V and V
REF
= 1 V for GTLP (unless otherwise noted) (see Figure 2)
MIN MAX UNIT
f
clock
Clock frequency 85 MHz
LEAB or LEBA high 3.3
twPulse duration
CLKAB or CLKBA high or low 5.7
ns
A before CLKAB↑ 1
B before CLKBA↑ 1.8
p
A before LEAB↓ 0.5
tsuSetup time
B before LEBA↓ 1.2
ns
CEAB before CLKAB↑ 1.2
CEBA before CLKBA↑ 1.4
A after CLKAB↑ 1.9
B after CLKBA↑ 0.5
A after LEAB↓ 2.7
thHold time
B after LEBA↓ 3.5
ns
CEAB after CLKAB↑ 1.2
CEBA after CLKBA↑ 1.1
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, V
TT
= 1.5 V and V
REF
= 1 V for GTLP (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN TYP†MAX UNIT
f
max
85 MHz
A 2.5 6.9
t
pd
LEAB
B
3.2 7.3
ns
CLKAB 3.4 7.8
t
en
2.8 7
t
dis
OEAB
B
2.8 7
ns
t
r
Transition time, B outputs (20% to 80%) 2.6 ns
t
f
Transition time, B outputs (80% to 20%) 2.6 ns
B 1.5 5.7
t
pd
LEBA
A
1.8 5.7
ns
CLKBA 2.3 5.5
t
en
1.8 6.1
t
dis
OEBA
A
1.8 6.1
ns
†
All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C.
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
S1
6 V
Open
GND
500 Ω
500 Ω
TEST
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
S1
Open
6 V
GND
t
PLH
t
PHL
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
3 V
0 V
V
REF
V
REF
V
TT
V
OL
0 V
VOL + 0.3 V
VOH – 0.3 V
≈0 V
3 V
0 V
0 V
3 V
0 V
t
w
Input
3 V
3 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A port to B port)
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
Timing
Input
Data Input
A Port
Output
Input
V
TT
Test
Point
CL = 30 pF
(see Note A)
From Output
Under Test
25 Ω
LOAD CIRCUIT FOR B OUTPUTS
t
PLH
t
PHL
0 V
V
OH
V
OL
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
Output
V
TT
V
REF
V
REF
V
REF
V
REF
0 V
V
TT
Data Input
B Port
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
Figure 2. Load Circuits and Voltage Waveforms
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The previous switching characteristics table shows the switching characteristics of the device into a lumped load
(Figure 2). However, the designer’s backplane application most likely is a distributed load, the physical representation
as shown in Figure 3. This backplane, or distributed load, can be closely approximated to an RLC circuit, as in
Figure 4. This device has been designed for optimum performance into this RLC circuit. The following switching
characteristics table shows the switching characteristics of the device into the RLC load, to help the designer better
understand the performance of the GTLP device in this typical backplane. See www.ti.com/sc/gtlp for more
information.
Drvr
1.5 V
.25” 2”
1” 1”
1.5 V
1”1”
2” .25”
Rcvr
Rcvr
Rcvr
Figure 3. Medium-Drive Test Backplane
Slot 1 Slot 2 Slot 9 Slot 10
Conn.
Conn. Conn. Conn.
Z0 = 70 Ω
38 Ω
38 Ω
From Output
Under Test
Test
Point
1.5 V
CL = 9 pF
19 Ω
LL = 19 nH
Figure 4. Medium-Drive RLC Network
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, V
TT
= 1.5 V and V
REF
= 1 V for GTLP (see Figure 4)
†
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN TYP‡UNIT
f
max
85 MHz
A 3.6
t
pd
LEAB
B
4.3
ns
CLKAB 4.4
t
en
4.1
t
dis
OEAB
B
4.3
ns
t
r
Rise time, B outputs (20% to 80%) 1.4 ns
t
f
Fall time, B outputs (80% to 20%) 2.1 ns
†
TI SPICE simulation data
‡
All typical values are at VCC = 3.3 V, TA = 25°C.
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