TEXAS INSTRUMENTS SN74GTLPH1655 Technical data
SN74GTLPH1655
16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294 – OCTOBER 1999
D
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D
Bidirectional Interface Between GTL+
Signal Levels and LVTTL Logic Levels
D
Partitioned as Two 8-Bit Transceivers With
Individual Latch Timing and Output Control
but With a Common Clock
D
LVTTL Interfaces Are 5-V Tolerant
D
High-Drive GTL+ Outputs (100 mA)
D
LVTTL Outputs (–24 mA/24 mA)
D
Variable Edge-Rate Control (ERC) Input
Selects GTL+ Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity
D
I
, Power-Up 3-State, and BIAS V
off
Support Live Insertion
D
Bus Hold on A-Port Data Inputs
D
Distributed VCC and GND-Pin Configuration
Minimizes High-Speed Switching Noise
D
Package Option Includes Plastic Thin
Shrink Small-Outline Package
description
The SN74GTLPH1655 is a high-drive 16-bit
universal bus transceiver (UBT) that provides
LVTTL-to-GTL+ and GTL+-to-LVTTL signal-level
translation. It is partitioned as two 8-bit
transceivers and allows for transparent, latched,
and clocked modes of data transfer similar to the
’16501 function. The device provides a
high-speed interface between cards operating at
LVTTL logic levels and a backplane operating at
GTL+ signal levels. High-speed (about two times
faster than standard LVTTL or TTL) backplane
operation is a direct result of GTLP’s reduced
output swing (<1 V), reduced input threshold
levels, improved differential input, and output
edge control (OEC). Improved GTLP OEC
circuits minimize bus settling time and have been
designed and tested using several backplane
models. The high drive is suitable for driving
double-terminated low-impedance backplanes
using incident-wave switching.
CC
1OEAB
1OEBA
V
CC
1A1
GND
1A2
1A3
GND
1A4
GND
1A5
GND
1A6
1A7
V
CC
1A8
2A1
GND
2A2
2A3
GND
2A4
2A5
GND
2A6
GND
2A7
V
CC
2A8
GND
2OEAB
2OEBA
DGG PACKAGE
(TOP VIEW)
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
CLK
1LEAB
1LEBA
ERC
GND
1B1
1B2
GND
1B3
1B4
1B5
GND
1B6
1B7
V
CC
1B8
2B1
GND
2B2
2B3
GND
2B4
2B5
V
REF
2B6
GND
2B7
2B8
BIAS V
2LEAB
2LEBA
OE
CC
PRODUCT PREVIEW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC and UBT are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN74GTLPH1655
16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294 – OCTOBER 1999
description (continued)
GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3.
The AC specification of the SN74GTLPH1655 is given only at the preferred higher noise margin GTL+, but the
user has the flexibility of using this device at either GTL (VTT = 1.2 V and V
and V
= 1 V) signal levels.
REF
Normally, the B port operates at GTL or GTL+ levels, while the A-port and control inputs are compatible with
LVTTL logic levels and are 5-V tolerant. V
This device is fully specified for live-insertion applications using I
is the reference input voltage for the B port.
REF
, power-up 3-state, and BIAS VCC. The I
off
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between GND and VCC adjusts the B-port output rise and fall times. This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
Active bus-hold circuitry holds unused or undriven L VTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
= 0.8 V) or GTL+ (VTT = 1.5 V
REF
off
When VCC is between 0 and 1.5 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to V
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
The SN74GTLPH1655 is characterized for operation from –40°C to 85°C.
functional description
The SN74GTLPH1655 is a high-drive (100 mA) 16-bit UBT containing D-type latches and D-type flip-flops for
data-path operation in transparent, latched, or clocked modes and is similar to a ’16501 function. The device
is uniquely partitioned as two 8-bit transceivers with individual latch timing and output signals and a common
PRODUCT PREVIEW
clock for both transceiver words. It can replace any of the functions shown in Table 1.
Table 1. SN74GTLPH1655 UBT Replacement Functions
FUNCTION 8 BIT 9 BIT 10 BIT 16 BIT
Transceiver ’245, ’623, ’645 ’863 ’861 ’16245, ’16623
Buffer/driver ’241, ’244, ’541 ’827 ’16241, ’16244, ’16541
Latched transceiver ’543 ’16543
Latch ’373, ’573 ’843 ’841 ’16373
Registered transceiver ’646, ’652 ’16646, ’16652
Flip-flop ’374, ’574 ’821 ’16374
CC
SN74GTLPH1655 UBT replaces all above functions
Data flow for each word is determined by the respective latch enables (xLEAB and xLEBA), output enables
(xOEAB
and xOEBA), and clock (CLK). The output enables (1OEAB, 1OEBA, 2OEAB, and 2OEBA) control
byte 1 and byte 2 data for the A-to-B and B-to-A directions, respectively. Note that CLK is common to both
directions and both 8-bit words. OE also is common and disables all I/O ports simultaneously.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MODE
SN74GTLPH1655
16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294 – OCTOBER 1999
functional description (continued)
For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB transitions
low, the A data is latched independent of CLK high or low. If LEAB is low, the A data is registered on the CLK
low-to-high transition. When OEAB is low, the outputs are active. With OEAB high, the outputs are in the
high-impedance state.
Data flow for the B-to-A direction is identical, but uses OEBA
Function Tables
FUNCTION
INPUTS
OEAB LEAB CLK A
H X X X Z Isolation
L HXL L Transparent
L HXH H Transparent
L L ↑ LLRegistered
L L ↑ HH Registered
L LHXB
L L L X B
†
A-to-B data flow is shown. B-to-A flow is similar but uses OEBA,
LEBA, and CLK.
‡
Output level before the indicated steady-state input conditions were
established, provided that CLK was high before LEAB went low
§
Output level before the indicated steady-state input conditions were
established
OUTPUT ENABLE
INPUTS
OE OEAB OEBA A PORT B PORT
L L L Active Active
L LH ZActive
L H L Active Z
L HH Z Z
H X X Z Z
†
OUTPUT
B
0
0
OUTPUTS
, LEBA, and CLK.
‡
Previous state
§
Previous state
PRODUCT PREVIEW
B-PORT EDGE-RATE CONTROL (ERC)
INPUT ERC
LOGIC
LEVEL
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NOMINAL
VOLTAGE
H V
L GND Fast
CC
OUTPUT
B-PORT
EDGE RATE
Slow
3
SN74GTLPH1655
16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294 – OCTOBER 1999
logic diagram (positive logic)
V
REF
ERC
CLK
1LEAB
1LEBA
1OEBA
1OEAB
OE
1A1
41
61
64
63
62
2
1
33
4
CLK
1D
C1
1D
C1
CLK
59
1B1
PRODUCT PREVIEW
To Seven Other Channels
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Loading...