TEXAS INSTRUMENTS SN74GTLPH1612 Technical data
SN74GTLPH1612
18-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES287 – OCTOBER 1999
D
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
D
Bidirectional Interface Between GTL+
Signal Levels and LVTTL Logic Levels
D
Equivalent to ’16601 Function
D
LVTTL Interfaces Are 5-V Tolerant
D
High-Drive GTL+ Outputs (100 mA)
D
LVTTL Outputs (–24 mA/24 mA)
D
Variable Edge-Rate Control (ERC) Input
Selects GTL+ Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity
D
I
, Power-Up 3-State, and BIAS V
off
Support Live Insertion
D
Bus Hold on A-Port Data Inputs
D
Distributed VCC and GND-Pin Configuration
Minimizes High-Speed Switching Noise
D
Packaged in Plastic Thin Shrink
Small-Outline Package
description
The SN74GTLPH1612 is a high-drive 18-bit
universal bus transceiver (UBT) that provides
LVTTL-to-GTL+ and GTL+-to-LVTTL signal-level
translation. It allows for transparent, latched,
clocked, or clock-enabled modes of data transfer
identical to the ’16601 function. The device
provides a high-speed interface between cards
operating at LVTTL logic levels and a backplane
operating at GTL+ signal levels. High-speed
(about two times faster than standard TTL or
LVTTL) backplane operation is a direct result of
GTLP’s reduced output swing (<1 V), reduced
input threshold levels, improved differential input,
and output edge control (OEC). Improved GTLP
OEC circuits minimize bus settling time and have
been designed and tested using several
backplane models. The high drive is suitable for
driving double-terminated low-impedance
backplanes using incident-wave switching.
CC
DGG PACKAGE
OEAB
LEAB
A1
A2
GND
A3
V
CC
A4
A5
GND
A6
A7
A8
GND
A9
V
CC
A10
GND
A11
A12
GND
A13
A14
GND
A15
V
CC
A16
ERC
A17
A18
OEBA
LEBA
(TOP VIEW)
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
CEAB
CLKAB
B1
B2
GND
B3
BIAS V
B4
B5
GND
B6
B7
B8
GND
B9
V
CC
B10
GND
B11
B12
GND
B13
B14
GND
B15
V
REF
B16
GND
B17
B18
CLKBA
CEBA
CC
PRODUCT PREVIEW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC and UBT are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN74GTLPH1612
18-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES287 – OCTOBER 1999
description (continued)
GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3.
The AC specification of the SN74GTLPH1612 is given only at the preferred higher noise margin GTL+, but the
user has the flexibility of using this device at either GTL (VTT = 1.2 V and V
and V
= 1 V) signal levels.
REF
Normally, the B port operates at GTL or GTL+ levels, while the A-port and control inputs are compatible with
LVTTL logic levels and are 5-V tolerant. V
This device is fully specified for live-insertion applications using I
is the reference input voltage for the B port.
REF
, power-up 3-state, and BIAS VCC. The I
off
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between GND and VCC adjusts the B-port output rise and fall times. This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
Active bus-hold circuitry is provided to hold unused or undriven L VTTL inputs at a valid logic state. Use of pullup
or pulldown resistors with the bus-hold circuitry is not recommended.
= 0.8 V) or GTL+ (VTT = 1.5 V
REF
off
When VCC is between 0 and 1.5 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to V
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
The SN74GTLPH1612 is characterized for operation from –40°C to 85°C.
functional description
The SN74GTLPH1612 is a high-drive (100 mA) 36-bit UBT containing D-type latches and D-type flip-flops for
data-path operation in transparent, latched, clocked, or clock-enabled modes and can replace any of the
functions shown in Table 1.
PRODUCT PREVIEW
FUNCTION 8 BIT 9 BIT 10 BIT 16 BIT 18 BIT
Transceiver ’245, ’623, ’645 ’863 ’861 ’16245, ’16623 ’16863
Buffer/Driver ’241, ’244, ’541 ’827 ’16241, ’16244, ’16541 ’16825
Latched transceiver ’543 ’16543 ’16472
Latch ’373, ’573 ’843 ’841 ’16373 ’16843
Registered transceiver ’646, ’652 ’16646, ’16652 ’16474
Flip-flop ’374, ’574 ’821 ’16374
Standard UBT ’16500, ’16501
Universal bus driver ’16835
Registered transceiver with CLK enable ’2952 ’16470, ’16952
Flip-flop with CLK enable ’377 ’823 ’16823
Standard UBT with CLK enable ’16600, ’16601
Table 1. SN74GTLPH1612 UBT Replacement Functions
CC
SN74GTLPH1612 UBT replaces all above functions
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MODE
Latched storage of A data
Transparent
Clocked storage of A data
SN74GTLPH1612
18-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES287 – OCTOBER 1999
functional description (continued)
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by clock-enable (CEAB and CEBA) inputs.
OEAB and OEBA control the 18 bits of data for the A-to-B and B-to-A directions, respectively.
For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the
A data is latched if CEAB
in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is low, the outputs
are active. When OEAB is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that for A to B, buses OEBA, LEBA, CLKBA, and CEBA.
is low and CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored
Function Tables
OUTPUT ENABLE
INPUTS
CEAB OEAB LEAB CLKAB A
X H X X X Z Isolation
L L L H X B
L LL LXB
X L H X L L
X LH XH H
L L L ↑ L L
L LL ↑ HH
H L L X X B
†
A-to-B data flow is shown: B-to-A data flow is similar but uses OEBA, LEBA, CLKBA,
and CEBA
‡
Output level before the indicated steady-state input conditions were established, provided
that CLKAB was high before LEAB went low
§
Output level before the indicated steady-state input conditions were established
.
B-PORT EDGE-RATE CONTROL (ERC
INPUT ERC
LOGIC
LEVEL
L GND Slow
H
NOMINAL
VOLTAGE
V
CC
†
OUTPUT
B
‡
0
§
0
§
0
OUTPUT
B-PORT
EDGE RATE
p
Clock inhibit
)
Fast
PRODUCT PREVIEW
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74GTLPH1612
18-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES287 – OCTOBER 1999
logic diagram (positive logic)
V
REF
ERC
OEAB
CEAB
CLKAB
LEAB
LEBA
CLKBA
CEBA
OEBA
A1
39
28
1
64
63
2
32
34
33
31
3
CLK
CE
1D
C1
CE
1D
C1
CLK
62
B1
PRODUCT PREVIEW
4
To 17 Other Channels
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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