Texas Instruments SN74GTLP1394D, SN74GTLP1394DGVR, SN74GTLP1394DR Datasheet
SN74GTLP1394
2-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SELECTABLE POLARITY
SCES286 – OCTOBER 1999
D
Bidirectional Interface Between GTL+
Signal Levels and LVTTL Logic Levels
D
LVTTL Interfaces Are 5-V Tolerant
D
High-Drive GTL+ Outputs (100 mA)
D
LVTTL Outputs (–24 mA/24 mA)
D
Variable Edge-Rate Control (ERC) Input
Selects GTL+ Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity
D
I
, Power-Up 3-State, and BIAS V
off
CC
D, DGV, OR PW PACKAGE
(TOP VIEW)
OEBY
Y1
Y2
V
CC
A1
A2
OEAB
ERC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BIAS V
GND
B1
GND
B2
GND
V
T/C
CC
REF
Support Live Insertion
D
Polarity Control Selects True or
Complementary Outputs
D
Package Options Include Plastic
Small-Outline (D), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages
description
The SN74GTLP1394 is a high-drive 2-bit 3-wire bus transceiver that provides LVTTL-to-GTL+ and
GTL+-to-LVTTL signal-level translation. It allows for transparent and inverted transparent modes of data
transfer with separate L VTTL input and LVTTL output pins. The device provides a high-speed interface between
cards operating at LVTTL logic levels and a backplane operating at GTL+ signal levels and is especially
designed to work with the Texas Instruments TSB14C01A 1394 Backplane Physical-Layer Controller.
High-speed (about two times faster than standard LVTTL or TTL) backplane operation is a direct result of
GTLP’s reduced output swing (<1 V), reduced input threshold levels, improved differential input, and output
edge control (OEC). Improved GTLP OEC circuits minimize bus settling time and have been designed and
tested using several backplane models. The high drive is suitable for driving double-terminated low-impedance
backplanes using incident-wave switching.
GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3.
The AC specification of the SN74GTLP1394 is given only at the preferred higher noise margin GTL+, but the
user has the flexibility of using this device at either GTL (V
and V
= 1 V) signal levels.
REF
= 1.2 V and V
TT
= 0.8 V) or GTL+ (V
REF
Normally , the B port operates at GTL or GTL+ levels. The A inputs, Y outputs, and control inputs are compatible
with LVTTL logic levels and are 5-V tolerant. V
This device is fully specified for live-insertion applications using I
is the reference input voltage for the B port.
REF
, power-up 3-state, and BIAS VCC. The I
off
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS V
circuitry precharges and preconditions the B-port
CC
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between GND and VCC adjusts the B-port output rise and fall times. This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Copyright 1999, Texas Instruments Incorporated
TT
= 1.5 V
PRODUCT PREVIEW
off
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN74GTLP1394
OPERATION OR FUNCTION
MODE
2-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SELECTABLE POLARITY
SCES286 – OCTOBER 1999
description (continued)
When VCC is between 0 and 1.5 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to V
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
The SN74GTLP1394 is characterized for operation from –40°C to 85°C.
functional description
The output-enable (OEAB) input controls the activity of the B port. When OEAB is low, the B-port outputs are
active. When OEAB is high, the B-port outputs are disabled.
Separate input and output pins allow the device to transmit and receive simultaneously. The OEBY input
controls the Y outputs. When OEBY is low, the Y outputs are active. When OEBY is high, the Y outputs are
disabled.
The polarity-control (T/C) input is provided to select polarity of data transmission in both directions. When T/C
is high, data transmission is true, and A data goes to the B bus and B data goes to the Y bus. When T/C is low,
data transmission is complementary, and A data goes to the B bus and B data goes to the Y bus.
CC
INPUTS
T/C OEAB OEBY
X H H Z Isolation
H L H A data to B bus True driver
H H L B data to Y bus True driver
H L L A data to B bus, B data to Y bus True transceiver
L LH A data to B bus Inverted driver
L HL B data to Y bus Inverted driver
L L L A data to B bus, B data to Y bus Inverted transceiver
PRODUCT PREVIEW
Function Tables
OUTPUT ENABLE
OUTPUT EDGE-RATE CONTROL (ERC)
INPUT ERC
LOGIC
LEVEL
NOMINAL
VOLTAGE
L GND Slow
H
V
CC
OUTPUT
B-PORT
EDGE RATE
Fast
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
logic diagram (positive logic)
SN74GTLP1394
WITH SELECTABLE POLARITY
SCES286 – OCTOBER 1999
V
REF
ERC
OEAB
T/C
OEBY
A1
Y1
A2
Y2
10
8
7
9
1
5
2
6
3
14
12
B1
B2
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC and BIAS VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1): A and control inputs –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port, ERC
Voltage range applied to any output in the high-impedance or power-off state, V
(see Note 1):Y –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
(see Note 1):Y –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: Y 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
O
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
(see Note 3): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
, and V
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
REF
O
O
B port 200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2) 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
PRODUCT PREVIEW
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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