Texas Instruments SN74GTL16616DGGR, SN74GTL16616DL, SN74GTL16616DLR Datasheet

SN54GTL16616, SN74GTL16616

17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS

WITH BUFFERED CLOCK OUTPUTS

SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999

D

Members of the Texas Instruments

Widebus

D

Universal Bus Transceiver (

 Family

UBT

Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode

D

GTL Buffered CLKAB Signal (CLKOUT)

D

Translate Between GTL/GTL+ Signal Levels
and LVTTL Logic Levels

D

Support Mixed-Mode (3.3 V and 5 V) Signal
Operation on A-Port and Control Inputs

D

Equivalent to ’16601 Function

D

I

Supports Partial-Power-Down Mode

off

Operation

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors on A Port

D

Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II

D

Distributed VCC and GND-Pin Configuration
Minimizes High-Speed Switching Noise

D

Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Ceramic Flat
(WD) Packages

description

The ’GTL16616 devices are 17-bit universal
bus transceivers (UBTs) that provide

)

SN54GTL16616 . . . WD PACKAGE

SN74GTL16616 . . . DGG OR DL PACKAGE

OEAB

LEAB

V

(3.3 V)

CC

V

(3.3 V)

CC

CLKIN

OEBA

LEBA

A1

GND

A2
A3

A4
A5
A6

GND

A7
A8
A9

A10

A11

A12

GND

A13
A14
A15

A16
A17

GND

(TOP VIEW)

1

56

2

55

3

54

4

53

5

52

6

51

7

50

8

49

9

48

10

47

11

46

12

45

13

44

14

43

15

42

16

41

17

40

18

39

19

38

20

37

21

36

22

35

23

34

24

33

25

32

26

31

27

30

28

29

CEAB
CLKAB
B1
GND
B2
B3
V

(5 V)

CC

B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V

REF

B16
B17
GND
CLKOUT
CLKBA
CEBA

LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL
signal-level translation. They combine D-type
flip-flops and D-type latches to allow for transparent, latched, clocked, and clocked-enabled modes of data
transfer identical to the ’16601 function. Additionally, they provide for a copy of CLKAB at GTL/GTL+ signal
levels (CLKOUT) and conversion of a GTL/GTL+ clock to L VTTL logic levels (CLKIN). The devices provide an
interface between cards operating at L VTTL logic levels and a backplane operating at GTL/GTL+ signal levels.
Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and
output edge control (OEC).

The user has the flexibility of using this device at either GTL (V
higher noise margin GTL+ (VTT = 1.5 V and V

= 1 V) signal levels. GTL+ is the T exas Instruments derivative

REF

= 1.2 V and V

TT

= 0.8 V) or the preferred

REF

of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V
tolerant. V
V

(3.3 V) supplies the LVTTL output buffers.

CC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus, OEC, and UBT are trademarks of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

is the reference input voltage for the B port. VCC (5 V) supplies the internal and GTL circuitry while

REF

Copyright  1999, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54GTL16616, SN74GTL16616

MODE

Latched storage of A data

Transparent

Clocked storage of A data

17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
WITH BUFFERED CLOCK OUTPUTS

SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999

description (continued)

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB and CEBA)
inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is
low, the A data is latched if CEAB
data is stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is
low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B
to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CEBA.

is low and CLKAB is held at a high or low logic level. If LEAB is low, the A-bus

These devices are fully specified for partial-power-down applications using I

. The I

off

circuitry disables the

off

outputs, preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven L VTTL inputs at a valid logic state. Use of pullup or pulldown

resistors with the bus-hold circuitry is not recommended.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54GTL16616 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74GTL16616 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

CEAB OEAB LEAB CLKAB A

X H X X X Z Isolation
L L L H or L X B
L L L H or L X B
X L H X L L
X LH XH H
L L L ↑ L L
L LL ↑ HH
H L L X X B

†

A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA,
and CEBA

‡

Output level before the indicated steady-state input conditions were established, provided
that CLKAB was high before LEAB went low

§

Output level before the indicated steady-state input conditions were established

.

†

OUTPUT

B

‡

0

§

0

§

0

p

Clock inhibit

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

35

V

REF

SN54GTL16616, SN74GTL16616

17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS

WITH BUFFERED CLOCK OUTPUTS

SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999

OEAB

CEAB

CLKAB

LEAB

LEBA

CLKBA

CEBA

OEBA

A1

1

56

55

2

28

30

29

27

3

CLK

CE

1D
C1

CE

1D
C1

CLK

1 of 17 Channels

54

B1

CLKIN

26

31

CLKOUT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54GTL16616, SN74GTL16616

UNIT

VCCSuppl

oltage

V

V

V

V

Suppl

oltage

V

VIInput voltage

V

V

g

V

V

V

I

mA

17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
WITH BUFFERED CLOCK OUTPUTS

SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC: 3.3 V –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 V –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V
Voltage range applied to any output in the high or power-off state, V

(see Note 1): A port –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the low state, I
Current into any A-port output in the high state, I

Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I
Output clamp current, I

Package thermal impedance, θJA (see Note 3): DGG package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and VO > VCC.

3. The package thermal impedance is calculated in accordance with JESD 51.

(see Note 1): A-port and control inputs –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . .

I

B port and V

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REF

O

B port –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

: A port 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

B port 80 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2) 64 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

OK

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

DL package 56°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

†

recommended operating conditions (see Notes 4 through 6)

SN54GTL16616 SN74GTL16616

MIN NOM MAX MIN NOM MAX

pp

y v

Termination

TT

voltage

pp

REF

IH

IL

I

IK

I

OH

OL

T

A

NOTES: 4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

y v

p

High-level
input voltage

Low-level
input voltage

Input clamp current –18 –18 mA
High-level

output current
Low-level

output current
Operating free-air temperature –55 125 –40 85 °C

Implications of Slow or Floating CMOS Inputs

5. Normal connection sequence is GND first, VCC = 5 V second, and VCC = 3.3 V , I/O, control inputs, VTT and V

6. VTT and RTT can be adjusted to accommodate backplane impedances as long as they do not exceed the DC absolute IOL ratings.
Similarly , V

3.3 V 3.15 3.3 3.45 3.15 3.3 3.45
5 V 4.75 5 5.25 4.75 5 5.25
GTL 1.14 1.2 1.26 1.14 1.2 1.26
GTL+
GTL 0.74 0.8 0.87 0.74 0.8 0.87
GTL+ 0.87 1 1.1 0.87 1 1.1
B port V
Except B port 5.5 5.5
B port V
Except B port
B port V
Except B port

A port –32 –32 mA
A port 64 64

B port

can be adjusted to optimize noise margins, but normally is 2/3 VTT.

REF

1.35 1.5 1.65 1.35 1.5 1.65

TT

+50 mV V

REF

2 2

–50 mV V

REF

0.8 0.8

40 40

, literature number SCBA004.

REF

+50 mV

REF

V

TT

–50 mV

REF

(any order) last.

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265