Texas Instruments SN74GTL16612DGGR, SN74GTL16612DL, SN74GTL16612DLR Datasheet
SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480I – JUNE 1994 – REVISED NOVEMBER 1999
D
Members of the Texas Instruments
Widebus
D
Universal Bus Transceiver (
Family
UBT
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
D
Translate Between GTL/GTL+ Signal Levels
and LVTTL Logic Levels
D
Support Mixed-Mode (3.3 V and 5 V) Signal
Operation on A-Port and Control Inputs
D
Identical to ’16601 Function
D
I
Supports Partial-Power-Down Mode
off
Operation
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors on A Port
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
D
Distributed VCC and GND-Pin Configuration
Minimizes High-Speed Switching Noise
D
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Ceramic Flat
(WD) Packages
description
The ’GTL16612 devices are 18-bit universal bus
transceivers (UBT) that provide LVTTL-toGTL/GTL+ and GTL/GTL+-to-LVTTL signal-level
translation. They combine D-type flip-flops and
)
SN54GTL16612 . . . WD PACKAGE
SN74GTL16612 . . . DGG OR DL PACKAGE
OEAB
LEAB
V
(3.3 V)
CC
V
(3.3 V)
CC
OEBA
LEBA
A1
GND
A2
A3
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
A16
A17
GND
A18
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
CEAB
CLKAB
B1
GND
B2
B3
V
(5 V)
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
REF
B16
B17
GND
B18
CLKBA
CEBA
D-type latches to allow for transparent, latched,
clocked, and clock-enabled modes of data transfer identical to the ’16601 function. The devices provide an
interface between cards operating at L VTTL logic levels and a backplane operating at GTL/GTL+ signal levels.
Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and
output edge control (OEC).
The user has the flexibility of using these devices at either GTL (V
higher noise margin GTL+ (VTT = 1.5 V and V
= 1 V) signal levels. GTL+ is the T exas Instruments derivative
REF
= 1.2 V and V
TT
= 0.8 V) or the preferred
REF
of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V
tolerant. V
(5 V) supplies the internal and GTL circuitry while VCC (3.3 V) supplies the LVTTL output buffers.
V
CC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT, and OEC are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
is the reference input voltage for the B port.
REF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN54GTL16612, SN74GTL16612
MODE
Latched storage of A data
Transparent
Clocked storage of A data
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480I – JUNE 1994 – REVISED NOVEMBER 1999
description (continued)
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable(LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB and CEBA)
inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is
low, the A data is latched if CEAB
data is stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is
low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B
to A is similar to that for A to B, but uses OEBA, LEBA, CLKBA, and CEBA.
is low and CLKAB is held at a high or low logic level. If LEAB is low, the A
These devices are fully specified for partial-power-down applications using I
. The I
off
circuitry disables the
off
outputs, preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven L VTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
The SN54GTL16612 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74GTL16612 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
CEAB OEAB LEAB CLKAB A
X H X X X Z Isolation
L L L H X B
L LL LXB
X L H X L L
X LH XH H
L L L ↑ L L
L LL ↑ HH
H L L X X B
†
A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA,
and CEBA
‡
Output level before the indicated steady-state input conditions were established, provided
that CLKAB was high before LEAB went low
§
Output level before the indicated steady-state input conditions were established
.
†
OUTPUT
B
‡
0
§
0
§
0
p
Clock inhibit
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480I – JUNE 1994 – REVISED NOVEMBER 1999
V
REF
OEAB
CEAB
CLKAB
LEAB
LEBA
CLKBA
CEBA
OEBA
A1
35
1
56
55
2
28
30
29
27
3
CLK
CE
1D
C1
CE
1D
C1
CLK
54
B1
To 17 Other Channels
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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