Texas Instruments SN74GTL16612ADGGR, SN74GTL16612ADL, SN74GTL16612ADLR Datasheet
SN54GTL16612A, SN74GTL16612A
18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS
SCES187D – JANUARY 1999 – REVISED DECEMBER 1999
D
Members of the Texas Instruments
Widebus
D
Universal Bus Transceiver (
Family
UBT
)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
D
Translate Between GTL/GTL+ Signal Levels
and LVTTL Logic Levels
D
Support Mixed-Mode (3.3-V and 5-V) Signal
Operation on A-Port and Control Inputs
D
B-Port Transition T ime Optimized for
Distributed Backplane Loads
D
I
Supports Partial-Power-Down Mode
off
Operation
description
The ’GTL16612A devices are 18-bit universal bus transceivers (UBT) that provide LVTTL-to-GTL+ and
GTL+-to-L VTTL signal-level translation. They allow for transparent, latched, clocked, or clock-enabled modes
of data transfer. These devices provide a high-speed interface between cards operating at LVTTL logic levels
and backplanes operating at GTL+ signal levels. High-speed (about two times faster than standard L VTTL or
TTL) backplane operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels,
and output edge control (OEC). Improved GTL+ OEC circuits minimize bus settling time and have been
designed and tested using several backplane models.
D
Bus Hold on A-Port Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Distributed VCC and GND-Pin Configuration
Minimizes High-Speed Switching Noise
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Ceramic Flat
(WD) Packages
V
TT
.25”
TT
R
V
TT
.875”
.625” .625”
Conn.
1” 1”
Rcvr
Slot 1 Slot 2
.625”.625”
Conn. Conn. Conn.
1”1”
Rcvr
Drvr
Slot 8
Rcvr
Slot 16
.25”
R
TT
1.8
1.6
1.4
1.2
1.0
Volts – V
0.8
0.6
0.4
020
TI GTL16612
Fairchild GTLP16612
TI GTL16612A
10 30
t – Time – ns
Figure 1. Test Backplane Model With Output Waveform Results
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI, OEC, UBT, and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN54GTL16612A, SN74GTL16612A
18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS
SCES187D – JANUARY 1999 – REVISED DECEMBER 1999
description (continued)
Figure 1 shows actual device output waveforms using a synchronous clock at 75 MHz. The test backplane is
a 16-slot, 14-inch board with loaded impedance of 33 Ω. VTT is 1.5 V , V
The driver is in slot 8, with receivers in alternate slots 1, 3, 5, 7, 10, 12, 14, and 16. Receiver slot 1 signals are
shown. The signal becomes progressively worse as the receiver moves closer to the driver or the spacing
between receiver cards is reduced. The clock is independent of the data and the system clock frequency is
limited by the backplane flight time to about 80–90 MHz. This frequency can be increased even more (30% to
40%) if the clock is generated and transmitted together with the data off the driver card (source synchronous).
is 1 V , and RTT pullup resistor is 50 Ω.
REF
Additional design considerations can be found in
Application Information
at the end of this data sheet.
These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in
transparent, latched, clocked, and clock-enabled modes. These UBTs can replace any of the functions shown
in Table 1.
Table 1. ’GTL16612A UBT Replacement Functions
FUNCTION 8 BIT 9 BIT 10 BIT 16 BIT 18 BIT
Transceiver ’245, ’623, ’645 ’863 ’861 ’16245, ’16623 ’16863
Buffer/driver ’241, ’244, ’541 ’827 ’16241, ’16244, ’16541 ’16825
Latched transceiver ’543 ’16543 ’16472
Latch ’373, ’573 ’843 ’841 ’16373 ’16843
Registered transceiver ’646, ’652 ’16646, ’16652 ’16474
Flip-flop ’374, ’574 ’821 ’16374
Standard UBT ’16500, ’16501
Universal bus driver ’16835
Registered transceiver with CLK enable ’2952 ’16470, ’16952
Flip-flop with CLK enable ’377 ’823 ’16823
Standard UBT with CLK enable ’16600, ’16601
’GTL16612A UBT replaces all above functions
GTL+ is the Texas Instruments (TI) derivative of the Gunning transceiver logic (GTL) JEDEC standard
JESD 8-3. The AC specification of the ’GTL16612A is given only at the preferred higher noise margin GTL+,
but this device can be used at either GTL (V
= 1.2 V and V
TT
= 0.8 V) or GTL+ (V
REF
= 1.5 V and V
TT
REF
= 1 V)
signal levels.
The B port normally operates at GTL or GTL+ levels, while the A-port and control inputs are compatible with
LVTTL logic levels and are 5-V tolerant. V
is the reference input voltage for the B port.
REF
T o improve signal integrity , the ’GTL16612A B-port output transition time is optimized for distributed backplane
loads.
(5 V) supplies the internal and GTL circuitry, while VCC (3.3 V) supplies the LVTTL output buffers.
V
CC
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock or latch enable can be controlled by the clock-enable (CEAB
and CEBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When
LEAB is low , the A data is latched if CEAB
is low and CLKAB is held at a high or low logic level. If LEAB is low,
the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB
is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for
B to A is similar to that for A to B, but uses OEBA, LEBA, CLKBA, and CEBA.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54GTL16612A, SN74GTL16612A
18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS
SCES187D – JANUARY 1999 – REVISED DECEMBER 1999
description (continued)
Active bus-hold circuitry holds unused or undriven L VTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
These devices are fully specified for partial-power-down applications using I
. The I
off
circuitry disables the
off
outputs, preventing damaging current backflow through the devices when they are powered down.
The SN54GTL16612A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74GTL16612A is characterized for operation from –40°C to 85°C.
SN54GTL16612A ...WD PACKAGE
SN74GTL16612A . . . DGG OR DL PACKAGE
OEAB
LEAB
V
(3.3 V)
CC
V
(3.3 V)
CC
OEBA
LEBA
A1
GND
A2
A3
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
A16
A17
GND
A18
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
CEAB
CLKAB
B1
GND
B2
B3
V
(5 V)
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
REF
B16
B17
GND
B18
CLKBA
CEBA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54GTL16612A, SN74GTL16612A
MODE
Latched storage of A data
Transparent
Clocked storage of A data
18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS
SCES187D – JANUARY 1999 – REVISED DECEMBER 1999
CEAB OEAB LEAB CLKAB A
X H X X X Z Isolation
L L L H X B
L LL LXB
X L H X L L
X LH XH H
L L L ↑ L L
L LL ↑ HH
H L L X X B
†
A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA,
and CEBA
‡
Output level before the indicated steady-state input conditions were established, provided
that CLKAB was high before LEAB went low
§
Output level before the indicated steady-state input conditions were established
.
logic diagram (positive logic)
V
OEAB
CEAB
35
REF
1
56
INPUTS
FUNCTION TABLE
OUTPUT
†
B
‡
0
§
0
p
§
0
Clock inhibit
CLKAB
LEAB
LEBA
CLKBA
CEBA
OEBA
A1
55
2
28
30
29
27
3
CLK
CE
1D
C1
CE
1D
C1
CLK
54
B1
4
To 17 Other Channels
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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