Texas Instruments SN74GTL1655DGGR Datasheet

SN54GTL1655, SN74GTL1655

16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS

WITH LIVE INSERTION

SCBS696E – JULY 1997 – REVISED NOVEMBER 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Members of the Texas Instruments

Widebus

 Family

D

UBT

 (Universal Bus Transceiver)

Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode

D

Translate Between GTL/GTL+ Signal Level
and LVTTL Logic Levels

D

High-Drive (100 mA),
Low-Output-Impedance (12 Ω) Bus
Transceiver (B Port)

D

Edge-Rate-Control Input Configures the
B-Port Output Rise and Fall Times

D

I

off

, Power-Up 3-State, and BIAS V

CC

Support Live Insertion

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors on A Port

D

Distributed VCC and GND-Pin Configuration
Minimizes High-Speed Switching Noise

D

Package Options Include Thin Shrink
Small-Outline (DGG) and Ceramic Quad
Flat (HV) Packages

description

The ’GTL1655 devices are high-drive (100 mA),
low-output-impedance (12 Ω) 16-bit universal bus
transceivers (UBT) that provide LVTTL-to­GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level
translation. They are partitioned as two 8-bit
transceivers and combine D-type flip-flops and
D-type latches to allow for transparent, latched,
and clocked modes of data transfer similar to the
’16501 function. These devices provide an
interface between cards operating at L VTTL logic
levels and a backplane operating at GTL/GTL+
signal levels. Higher-speed operation is a direct
result of the reduced output swing (<1 V), reduced
input threshold levels and output edge control
(OEC). The high drive is suitable for driving
double-terminated low-impedance backplanes
using incident-wave switching.

Copyright  1999, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus, UBT, and OEC are trademarks of Texas Instruments Incorporated.

SN74GTL1655 . . . DGG PACKAGE

(TOP VIEW)

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1OEAB
1OEBA

V

CC

1A1

GND

1A2
1A3

GND

1A4

GND

1A5

GND

1A6
1A7

V

CC

1A8
2A1

GND

2A2
2A3

GND

2A4
2A5

GND

2A6

GND

2A7

V

CC

2A8

GND
2OEAB
2OEBA

CLK
1LEAB
1LEBA
V

ERC

GND
1B1
1B2
GND
1B3
1B4
1B5
GND
1B6
1B7
V

CC

1B8
2B1
GND
2B2
2B3
GND
2B4
2B5
V

REF

2B6
GND
2B7
2B8
BIAS V

CC

2LEAB
2LEBA
OE

SN54GTL1655, SN74GTL1655
16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
WITH LIVE INSERTION

SCBS696E – JULY 1997 – REVISED NOVEMBER 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

The user has the flexibility of using this device at either GTL (VTT = 1.2 V and V

REF

= 0.8 V) or the preferred

higher noise margin GTL+ (VTT = 1.5 V and V

REF

= 1 V) signal levels. GTL+ is the T exas Instruments derivative
of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with L VTTL logic levels but are not 5-V
tolerant. V

REF

is the reference input voltage for the B port.

These devices are uniquely partitioned as two 8-bit transceivers with individual latch timing and output signals,
but with a common clock and output enable inputs for both transceiver words.

Data flow for each word is determined by the respective latch enables (xLEAB and xLEBA), output enables
(xOEAB and xOEBA), and clock (CLK). The output enables (1OEAB, 1OEBA, 2OEAB, and 2OEBA) control
byte 1 and byte 2 data for the A-to-B and B-to-A directions, respectively.

For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB transitions
low, the A data is latched independent of CLK high or low. If LEAB is low, the A data is registered on the CLK
low-to-high transition. When OEAB is low, the outputs are active. With OEAB high, the outputs are in the
high-impedance state.

Data flow for the B-to-A direction is identical, but uses OEBA, LEBA, and CLK. Note that CLK is common to both
directions and both 8-bit words. OE is also common and is used to disable all I/O ports simultaneously.

The ’GTL1655 is featured with adjustable edge-rate control (V

ERC

). Changing V

ERC

input voltage between GND
and VCC adjusts the B-port output rise and fall times. This allows the designer to optimize for various loading
conditions.

These devices are fully specified for live-insertion applications using I

off

, power-up 3-state, and BIAS VCC. The

I

off

circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS V

CC

circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.

When V

CC

is between 0 and 1.5 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven L VTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.

The SN54GTL1655 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74GTL1655 is characterized for operation from –40°C to 85°C.

SN54GTL1655, SN74GTL1655

16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS

WITH LIVE INSERTION

SCBS696E – JULY 1997 – REVISED NOVEMBER 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54GTL1655 . . . HV PACKAGE

(TOP VIEW)

GND

1A2

1A1

NC

GND

1B1

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

9876543216867666564636261

GND

2A7

2A8

GND

2OEAB

OE

2B8

2B7

GND

1OEAB

CLK

1LEAB

1LEBA

1OEBA

1B2

GND

2A6

NC

2OEBA

2LEBA

2LEAB

1A3

2B6

V

ERC

V

CC

GND

NC – No internal connection

CC

V

CC

BIAS V

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11
12
13
14
15
16
17
18
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20
21
22
23
24
25
26

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59
58
57
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51
50
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44

1A4

GND

1A5

GND

1A6
1A7

V

CC

1A8

NC

2A1

GND

2A2
2A3

GND

2A4
2A5

GND

1B3
1B4
1B5
GND
1B6
1B7
V

CC

1B8
NC
2B1
GND
2B2
2B3
GND
2B4
2B5
V

REF

SN54GTL1655, SN74GTL1655
16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
WITH LIVE INSERTION

SCBS696E – JULY 1997 – REVISED NOVEMBER 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Function Tables

FUNCTION

†

INPUTS

OUTPUT

OEAB LEAB CLK A

B

MODE

H X X X Z Isolation
L HXL L Transparent
L HXH H Transparent
L L ↑ LL Registered
L L ↑ HH Registered
L LHXB

0

‡

Previous State

L L L X B

0

§

Previous State

†

A-to-B data flow is shown. B-to-A flow is similar, but uses OEBA, LEBA,
and CLK.

‡

Output level before the indicated steady-state input conditions were
established, provided that CLK was high before LEAB went low

§

Output level before the indicated steady-state input conditions were
established

OUTPUT ENABLE

INPUTS

OUTPUTS

OE OEAB OEBA A PORT B PORT

L L L Active Active
L LH ZActive
L H L Active Z
L HH Z Z
H X X Z Z

B-PORT EDGE-RATE CONTROL (V

ERC

)

INPUT V

ERC

OUTPUT
LOGIC
LEVEL

NOMINAL

VOLTAGE

B PORT

EDGE RATE

H V

CC

Slow

L GND Fast

SN54GTL1655, SN74GTL1655

16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS

WITH LIVE INSERTION

SCBS696E – JULY 1997 – REVISED NOVEMBER 1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1D
C1

CLK

1D
C1

CLK

1B1

1OEAB

CLK

1LEAB

1LEBA

1OEBA

1A1

1

64

63

62

2

4

59

To Seven Other Channels

OE

33

Pin numbers shown are for the DGG package.

V

ERC

61

V

REF

41