D
Compatible With IEEE Std 1 194.1-1991
(BTL)
D
TTL A Port, Backplane Transceiver Logic
(BTL) B Port
D
Open-Collector B-Port Outputs Sink
100 mA
D
Isolated Logic-Ground and Bus-Ground
Pins Reduce Noise
D
BIAS VCC Pin Minimizes Signal Distortion
During Live Insertion or Withdrawal
D
D
D
D
RC PACKAGE
(TOP VIEW)
CC
SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
High-Impedance State During Power Up
and Power Down
B-Port Biasing Network Preconditions the
Connector and PC Trace to the BTL
High-Level Voltage
TTL Input Structures Incorporate Active
Clamping to Aid in Line Termination
Packaged in Plastic Quad Flatpack
GND
2AI1
2AI2
2AO2
GND
2AO3
GND
2AI3
3AI1
3AO1
GND
3AO2
GND
1AI1
GND
CC
1AO1
V
CC
3AO3
BG V
1OEA
BIAS V
3AI3
BG GND
OEB
2OEA
2AO1
52 51 50 49 48 47 46 45 44 43 42 41 40
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20 21 22 23 24 25 26
3AI2
1OEB
TCK
TDI
TDO
V
V
CC
CC
TMS
GND
3OEA
2OEB
1B1
39
38
37
36
35
34
33
32
31
30
29
28
27
3OEB
GND
2B1
GND
2B2
GND
2B3
GND
3B1
GND
3B2
GND
3B3
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN74FB2041A
FUNCTION
Isolation
B d
7-BIT TTL/BTL TRANSCEIVER
SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
description
The SN74FB2041A device is a 7-bit transceiver designed to translate signals between TTL and backplane
transceiver logic (BTL) environments. It is specifically designed to be compatible with IEEE Std 1 194.1-1991.
The B port operates at BTL signal levels. The open-collector B ports are specified to sink 100 mA. Two output
enables (OEB and OEB) are provided for the B outputs. When OEB is high and OEB is low, the B port is active
and reflects the inverse of the data present at the A-input pins. When OEB is low, OEB
than 2.1 V , the B port is turned off. The enable/disable logic partitions the device as two 3-bit sections and one
1-bit section.
The A port operates at TTL signal levels and has split input and output pins. The A outputs reflect the inverse
of the data at the B port when the A-port output enable (OEA) is high. When OEA is low or when VCC is less
than 2.1 V, the A outputs are in the high-impedance state.
Pins are allocated for the four-wire IEEE Std 1 149.1 (JT AG) test bus. TMS and TCK are not connected and TDI
is shorted to TDO.
BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC is not connected.
The SN74FB2041A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OEB OEB OEA
L X L
X HL
L X H
X HH
H L L AI data to B bus
H L H AI data to B bus, B data to AO bus
ata to AO bus
is high, or VCC is less
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
logic symbol
†
OEB
1OEA
1OEB
2OEA
2OEB
3OEA
3OEB
1AO1
1AI1
2AO1
2AI1
2AO2
2AI2
2AO3
2AI3
3AO1
3AI1
3AO2
3AI2
3AO3
3AI3
46
47
45
20
25
24
26
50
51
52
2
4
3
6
8
10
9
12
14
16
18
G1
EN2
1EN3
EN4
1EN5
EN6
1EN7
21
41
61
40
1B1
3
5
7
38
36
34
32
30
28
2B1
2B2
2B3
3B1
3B2
3B3
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
functional block diagram
46
OEB
1AI1
45
47
51
1OEB
1OEA
40
1B1
1AO1
2OEB
2OEA
2AI1
2AO1
2AI2
2AO2
2AI3
2AO3
3OEB
3OEA
3AI1
3AO1
50
25
20
2
52
3
4
8
6
26
24
9
10
38
36
34
32
2B1
2B2
2B3
3B1
14
3AI2
3AI3
12
18
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3AO2
3AO3
4
30
28
3B2
3B3
VIHHigh-level input voltage
V
VILLow-level input voltage
V
IOLLow-level output current
mA
SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI: Except B port –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B
port –1.2 V to 3.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any B output in the disabled or power-off state, VO –0.5 V to 3.5 V. . . . . . . . . . . . . .
Voltage range applied to any output in the high state, VO: A port –0.5 V to V
. . . . . . . . . . . . . . . . . . . . . . . .
CC
Input clamp current, IIK: Except B port –40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current applied to any single output in the low state, I
: A port 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
B port 200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
(see Note 1) 44°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 2)
MIN NOM MAX UNIT
V
CC,
BIAS VCC,
BG V
CC
I
IK
I
OH
T
A
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 4.5 5 5.5 V
p
p
Input clamp current –18 mA
High-level output current AO port –3 mA
p
Operating free-air temperature 0 70 °C
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
B port 1.62 2.3
Except B port 2
B port 0.75 1.47
Except B port 0.8
AO port 24
B port 100
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74FB2041A
V
V
VOHAO port
V
V
V
AO port
V
V
V
V
B
V
4.5 V
I
‡
A
I
V
I
065mA
C
V
0.5 V or 2.5 V
pF
C
pF
I
(BIAS VCC)
V
0 to 2 V
V
(BIAS VCC)
V
A
7-BIT TTL/BTL TRANSCEIVER
SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
IK
OL
I
I
I
IH
IL
I
OH
I
OZH
I
OZL
I
OZPU
I
OZPD
I
OS
CC
i
C
o
io
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
For I/O ports, the parameters IIH and IIL include the off-state output current.
§
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
B port VCC = 4.5 V, II = –18 mA –1.2
Except B port VCC = 4.5 V, II = –40 mA –0.5
p
p
port
Except B port VCC = 5.5 V, VI = 5.5 V 50 µA
‡
Except B port VCC = 5.5 V, VI = 2.7 V 50 µA
Except B port VCC = 5.5 V, VI = 0.5 V –50
B port
B port VCC = 0 to 5.5 V, VO = 2.1 V 100 µA
AO port VCC = 5.5 V, VO = 2.7 V 50 µA
AO port VCC = 5.5 V, VO = 0.5 V –50 µA
AO port VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V 50 µA
AO port VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V –50 µA
§
AO port VCC = 5.5 V, VO = 0 –30 –180 mA
AI port to B port
B port to AO port
AI port
Control inputs
AO port VO = 0.5 V or 2.5 V 5.5 pF
B port
per IEEE Std 1194.1-1991
= 4.5
CC
= 4.5
CC
=
CC
VCC = 5.5 V, VI = 0.75 V –100
= 5.5 V,
CC
=
I
VCC = 0 to 4.5 V 5
VCC = 4.5 V to 5.5 V 5
IOH = –1 mA
IOH = –3 mA 2.5 3.3
IOL = 20 mA
IOL = 24 mA 0.35 0.5
IOL = 80 mA 0.75 1.1
IOL = 100 mA 1.15
=
O
µ
45
3
3
p
p
live-insertion specifications over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN MAX UNIT
CC
V
I
O
6
B port VCC = 0, VI (BIAS VCC) = 5 V 1.62 2.1 V
O
B port
VCC = 0 to 4.5 V
VCC = 4.5 V to 5.5 V
VCC = 0, VB = 1 V, Vl (BIAS VCC) = 4.5 V to 5.5 V –1
VCC = 0 to 5.5 V, OEB = 0 to 0.8 V 100
VCC = 0 to 2.2 V, OEB = 0 to 5 V 100
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
=
B
,
l
= 4.5 V to 5.5
450
10
µ
µA
(INPUT)
(OUTPUT)
AI
B
ns
B
AO
ns
OEB
B
ns
OEB
B
ns
OEA
AO
ns
OEA
AO
ns
t
ns
SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
†
t
sk(p)
†
t
sk(o)
t
t
(pr)
†
Skew values are applicable for through mode only.
Pulse skew, AI to B or B to AO 0.5 ns
Pulse skew, AI to B or B to AO 0.4 ns
Rise time, 1.3 V to 1.8 V, B outputs 1 1.6 2.4 1 2.5
Fall time, 1.8 V to 1.3 V, B outputs 1 1.4 2.3 1 2.4
B-port input pulse rejection 1 1 ns
FROM
TO
VCC = 5 V,
TA = 25°C
MIN TYP MAX
2.3 3.9 5.1 2 5.6
2.6 4.1 5 2.5 5.3
2 3.6 4.8 1.7 5.3
2.3 3.8 4.9 2 6.4
3 4.6 5.8 2.6 6.3
3.1 4.7 6 3.1 6.2
2.7 4.3 5.6 2.6 5.8
2.7 4.2 5.3 2.5 6.4
1.5 3.2 5.2 1.5 5.2
1.1 2.8 5 1 5
1 2.4 3.9 1 4.2
2.2 3.8 5.6 1.7 5.8
MIN MAX UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
2.1 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
Input 1.5 V 1.5 V
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (A TO B)
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (B TO A)
500 Ω
500 Ω
t
PHL
t
PHL
1.5 V 1.5 V
7 V
S1
1.55 V1.55 V
1.55 V1.55 V
t
PLH
t
PLH
Open
3 V
0 V
V
OH
V
OL
2 V
1 V
V
OH
V
OL
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT FOR B OUTPUTS
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V 1.5 V
t
PZL
1.5 V
t
PZH
1.5 V
ENABLE AND DISABLE TIMES (A PORT)
VOLTAGE WAVEFORMS
16.5 Ω
Test
Point
Open
7 V
Open
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: TTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,
tf≤ 2.5 ns; BTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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