D
Compatible With IEEE Std 1 194.1-1991
(BTL)
D
TTL A Port, Backplane Transceiver Logic
(BTL) B Port
D
Open-Collector B-Port Outputs Sink
100 mA
D
Isolated Logic-Ground and Bus-Ground
Pins Reduce Noise
RC PACKAGE
(TOP VIEW)
CC
SN74FB2040
8-BIT TTL/BTL TRANSCEIVER
SCBS173I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
D
High-Impedance State During Power Up
and Power Down
D
BIAS VCC Pin Minimizes Signal Distortion
During Live Insertion or Withdrawal
D
B-Port Biasing Network Preconditions the
Connector and PC Trace to the BTL
High-Level Voltage
D
Packaged in Plastic Quad Flatpack
GND
AI2
AI3
AO3
GND
AO4
GND
AI4
AI5
AO5
GND
AO6
GND
AI1
GND
AO1
AO7
CC
V
CC
AI7
BG V
OEA
BIAS V
BG GND
OEB
AO8
AO2
52 51 50 49 48 47 46 45 44 43 42 41 40
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20 21 22 23 24 25 26
AI6
OEB
TDO
TCK
TDI
V
V
CC
CC
TMS
AI8
GND
GND
B1
39
38
37
36
35
34
33
32
31
30
29
28
27
B8
GND
B2
GND
B3
GND
B4
GND
B5
GND
B6
GND
B7
GND
description
The SN74FB2040 device is an 8-bit transceiver designed to translate signals between TTL and backplane
transceiver logic (BTL) environments.
The B
port operates at BTL-signal levels. The open-collector B ports are specified to sink 100 mA. Two output
enables (OEB and OEB) are provided for the B outputs. When OEB is high and OEB is low, the B port is active
and reflects the inverse of the data present at the A-input pins. When OEB is low, OEB is high, or VCC is less
than 2.1 V, the B port is turned off.
The A port operates at TTL-signal levels and has separate input and output pins. The A outputs reflect the
inverse of the data at the B port when the A-port output enable (OEA) is high. When OEA is low or when V
is less than 2.1 V, the A outputs are in the high-impedance state.
Pins are allocated for the four-wire IEEE Std 1 149.1 (JT AG) test bus. TMS and TCK are not connected and TDI
is shorted to TDO.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
CC
1
SN74FB2040
FUNCTION
Isolation
B data to AO b
8-BIT TTL/BTL TRANSCEIVER
SCBS173I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
description (continued)
BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC is not connected.
The SN74FB2040 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OEB OEB OEA
L X L
X HL
L X H
X HH
H L L AI data to B bus
H L H AI data to B bus, B data to AO bus
us
logic symbol
†
OEB
OEA
OEB
AO1
AI1
AO2
AI2
AO3
AI3
AO4
AI4
AO5
AI5
AO6
AI6
AO7
AI7
AO8
AI8
46
47
45
50
51
52
2
4
3
6
8
10
9
12
14
16
18
20
24
G1
EN2
1EN3
21
1
40
B1
3
38
36
34
32
30
28
26
B2
B3
B4
B5
B6
B7
B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CC
,
CC
,
Suppl
oltage
4.555.5
V
VIHHigh-level input voltage
V
VILLow-level input voltage
V
IOLLow-level output current
mA
functional block diagram
OEB
OEB
OEA
AO1
AI1
46
45
47
51
50
To Seven Other Channels
SN74FB2040
8-BIT TTL/BTL TRANSCEIVER
SCBS173I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
40
B1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI: Except B port –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port –1.2 V to 3.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any B output in the disabled or power-off state, VO –0.5 V to 3.5 V. . . . . . . . . . . . . .
Voltage range applied to any output in the high state, VO: A port –0.5 V to V
Input clamp current, I
: Except B port –40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
. . . . . . . . . . . . . . . . . . . . . . . .
CC
B port –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current applied to any single output in the low state, IO: A port 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port 200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
(see Note 1) 44°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 2)
MIN NOM MAX UNIT
V
, BIAS V
BG V
CC
I
IK
I
OH
T
A
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
,
pp
y v
p
p
Input clamp current –18 mA
High-level output current AO port –3 mA
p
Operating free-air temperature 0 70 °C
Implications of Slow or Floating CMOS Inputs
B port 1.62 2.3
Except B port 2
B port 0.75 1.47
Except B port 0.8
AO port 24
B port 100
, literature number SCBA004.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74FB2040
V
V
VOHAO port
V
MIN
V
AO port
V
MIN
V
V
B
V
MIN
I
‡
A
I
V
I
070mA
C
V
V
GND
pF
C
pF
I
(BIAS VCC)
V
V
(BIAS VCC)
V
A
8-BIT TTL/BTL TRANSCEIVER
SCBS173I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
IK
OL
I
I
I
IH
IL
I
OH
I
OZH
I
OZL
I
OZPU
I
OZPD
I
OS
CC
i
C
o
io
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
For I/O ports, the parameters IIH and IIL include the off-state output current.
§
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
B port VCC = MIN,
Except B port VCC = MIN,
p
p
port
Except B port VCC = 5.5 V, VI = 5.5 V 50 µA
‡
Except B port VCC = 5.5 V,
Except B port VCC = 5.5 V,
B port
B port VCC = 0 to 5.5 V, VO = 2.1 V 100 µA
AO port VCC = 5.5 V, VO = 2.7 V 50 µA
AO port VCC = 5.5 V, VO = 0.5 V –50 µA
A port VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V 50 µA
A port VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V –50 µA
§
AO port VCC = 5.5 V, VO = 0 –30 –180 mA
AI port to B port
B port to AO port
AI port
Control inputs
AO port VO = VCC or GND 6 pF
B port
per IEEE Std 1194.1-1991
=
CC
=
CC
=
CC
VCC = 5.5 V,
= 5.5 V,
CC
=
or
I
CC
VCC = 0 to 4.5 V
VCC = 4.5 V to 5.5 V
II = –18 mA –1.2
II = –40 mA –0.5
IOH = –1 mA
IOH = –3 mA 2.5 3.3
IOL = 20 mA
IOL = 24 mA 0.35 0.5
IOL = 80 mA 0.75 1.1
IOL = 100 mA 1.15
VI = 2.7 V 50
VI = 0.5 V –50
VI = 0.75 V –100
=
O
40
3.5
3
µA
µ
p
5
p
5
live-insertion specifications over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN MAX UNIT
VCC = 0 to 4.5 V
VCC = 4.5 to 5.5 V
VCC = 0 ,
VCC = 0 to 5.5 V,
VCC = 0 to 2.2 V,
= 0 to 2 V,
B
VB = 1 V, VI (BIAS VCC) = 4.5 V to 5.5 V –1
OEB = 0 to 0.8 V 100
OEB = 0 to 5 V 100
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I
= 4.5 V to 5.5
4
V
I
CC
O
O
B port VCC = 0, VI (BIAS VCC) = 5 V 1.62 2.1 V
B port
450
10
µ
µA
(INPUT)
(OUTPUT)
AI
B
ns
B
AO
ns
OEB
B
ns
OEB
B
ns
OEA
AO
ns
OEA
AO
ns
SN74FB2040
8-BIT TTL/BTL TRANSCEIVER
SCBS173I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
sk(p)
t
sk(o)
t
r
t
f
B-port input pulse rejection 1 3.4 ns
Pulse skew, AI to B or B to AO 0.5 ns
Pulse skew, AI to B or B to AO 0.4 ns
Rise time, 1.3 V to 1.8 V, B port 2 2.8 3.8 1.7 ns
Fall time, 1.8 V to 1.3 V, B port 1 1.9 3 1 4.2 ns
FROM
TO
VCC = 5 V,
TA = 25°C
MIN TYP MAX
3.2 4.5 6 2.4 6.5
2.8 4.2 5.6 2.7 5.8
2.3 3.8 5.7 1.9 6.2
2.3 4.2 5.9 2 8.2
3.7 5.1 6.7 3 7
3.1 4.6 5.9 3 6.1
3.6 5.2 6.8 3.3 7
2.9 4.4 5.9 2.6 6.1
2.5 4 5.5 2.1 5.8
2.1 3.6 4.8 2 5
2.3 4.1 5.9 1.9 6.5
1.6 3.1 4.5 1.4 4.7
MIN MAX UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74FB2040
8-BIT TTL/BTL TRANSCEIVER
SCBS173I – NOVEMBER 1991 – REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
2.1 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
Input 1.5 V 1.5 V
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (A TO B)
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (B TO A)
500 Ω
500 Ω
t
PHL
t
PHL
1.5 V 1.5 V
7 V
S1
1.55 V1.55 V
1.55 V1.55 V
t
PLH
t
PLH
Open
3 V
0 V
V
OH
V
OL
2 V
1 V
V
OH
V
OL
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT FOR B OUTPUTS
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V 1.5 V
t
PZL
1.5 V
t
PZH
1.5 V
ENABLE AND DISABLE TIMES (A PORT)
VOLTAGE WAVEFORMS
16.5 Ω
Test
Point
Open
7 V
Open
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: TTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,
tf≤ 2.5 ns; BTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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