D
Compatible With IEEE Std 1 194.1-1991
(BTL)
D
TTL A Port, Backplane Transceiver Logic
(BTL) B Port
D
Open-Collector B-Port Outputs Sink
100 mA
D
BIAS VCC Pin Minimizes Signal Distortion
During Live Insertion or Withdrawal
9-BIT TTL/BTL COMPETITION TRANSCEIVER
D
D
D
D
RC PACKAGE
(TOP VIEW)
CC
SN74FB2032
SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999
High-Impedance State During Power Up
and Power Down
B-Port Biasing Network Preconditions the
Connector and PC Trace to the BTL
High-Level Voltage
TTL-Input Structures Incorporate Active
Clamping Networks to Aid in Line
Termination
Packaged in Plastic Quad Flatpack
GND
A3
GND
A4
GND
A5
GND
A6
GND
A7
GND
A8
GND
GND
GND
A1
WIN
CC
V
BIAS V
LE
CC
BG V
OEA
OEB
BG GND
COMPETE
A2
52 51 50 49 48 47 46 45 44 43 42 41 40
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20 21 22 23 24 25 26
AP
OEB
TDO
TCK
TDI
V
V
CC
CC
TMS
BP
GND
GND
B1
39
38
37
36
35
34
33
32
31
30
29
28
27
B8
GND
B2
GND
B3
GND
B4
GND
B5
GND
B6
GND
B7
GND
description
The SN74FB2032 device is a 9-bit transceiver designed to translate signals between TTL and backplane
transceiver logic (BTL) environments and to perform bus arbitration. It is designed specifically to be compatible
with IEEE Std 1194.1-1991.
The B port operates at BTL-signal levels. The open-collector B ports are specified to sink 100 mA and have
minimum output edge rates of 2 ns. Two output enables (OEB and OEB) are provided for the B outputs. When
OEB is low, OEB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
is high, or VCC is less than 2.1 V, the B port is turned off.
Copyright 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN74FB2032
9-BIT TTL/BTL COMPETITION TRANSCEIVER
SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999
description (continued)
The A port operates at TTL-signal levels. The A outputs reflect the inverse of the data at the B port when the
A-port output enable, OEA, is high. When OEA is low or when VCC is less than 2.1 V, the A outputs are in the
high-impedance state.
The A-port data is latched when the latch enable (LE) is high. When LE is low, the latches are transparent.
The Futurebus protocol logic can be activated by taking COMPETE low. The module (device) then compares
its A data (arbitration number) against the A data of another identical module also connected to the B arbitration
bus, and sets WIN high if the A data is greater than the A data of the other module (i.e., has higher priority). A8
and B8
during this operation, and the A bus of the first module wins priority , the A bus asserts its arbitration number on
the B-arbitration bus.
AP and BP are the bus-parity bits. The winning module can assert BP low if its parity bit (AP) is high.
In a typical operating sequence, a Futurebus arbitration controller latches its arbitration number into the A port
and waits for the results of a competition. When the competition is complete, and if the controller’s arbitration
number did not win, the controller reads back the current value of the B bus (by taking OEA high) and determines
the winning arbitration number. This allows the module to change its arbitration number for the next competition
cycle, if desired.
are the most-significant bits, and A1 and B1 are the least-significant bits. If OEB is high and OEB is low
Pins are allocated for the four-wire IEEE Std 1 149.1 (JT AG) test bus. TMS and TCK are not connected and TDI
is shorted to TDO.
BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC is not connected.
BG V
The SN74FB2032 is characterized for operation from 0°C to 70°C.
and BG GND are the supply inputs for the bias generator.
CC
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION
B d
Isolation
BP
SN74FB2032
9-BIT TTL/BTL COMPETITION TRANSCEIVER
SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999
Function Tables
TRANSCEIVER
INPUTS
OEA OEB OEB
L H L A data to B bus
H L X
H XH
H H L A data to B bus, B data to A bus
L L X
L X H
WIN
INPUTS
OEB
OEB COMPETE
H H X X L
H LH X L
H LLA1 < A2 L
H L L A2 ≤ A1 H
†
A1 refers to the A data of Module 1 and A2 refers to
the A data of Module 2. If LE = L, A = current A data.
If LE = H, A = the value of A8–A1 prior to the most
recent low-to-high transition of LE.
ata to A bus
DATA
†
A1, A2
WIN
BP
INPUTS
OEB OEB WIN AP
L X X X H
X HXXH
H LLXH
H LHLH
H L H H L
‡
If LE = L, AP = current AP data. If LE = H,
AP = the level of AP prior to the most
recent low-to-high transition of LE.
‡
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74FB2032
9-BIT TTL/BTL COMPETITION TRANSCEIVER
SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999
functional block diagram
46
OEB
45
OEB
47
OEA
AP
A8
A7
A6
A5
A4
14
12
10
8
6
4
D
C1
D
C1
D
C1
D
C1
D
C1
D
C1
24
26
28
30
32
34
BP
B8
B7
B6
B5
B4
A3
A2
A1
LE
COMPETE
2
52
50
18
20
D
C1
D
C1
D
C1
36
38
40
16
B3
B2
B1
WIN
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VIHHigh-level input voltage
V
VILLow-level input voltage
V
IOLLow-level output current
mA
SN74FB2032
9-BIT TTL/BTL COMPETITION TRANSCEIVER
SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI: Except BP, B port –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BP
, B port –1.2 V to 3.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any B output in the disabled or power-off state, VO –0.5 V to 3.5 V. . . . . . . . . . . . . .
Voltage range applied to any output in the high state, VO –0.5 V to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
Input clamp current, IIK: Except B port –40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current applied to any single output in the low state, I
: A port 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
B port 200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
(see Note 1) 44°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 2)
MIN NOM MAX UNIT
V
CC,
BIAS VCC,
BG V
CC
I
IK
I
OH
T
A
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 4.5 5 5.5 V
p
p
Input clamp current –18 mA
High-level output current AP, WIN, A port –3 mA
p
Operating free-air temperature 0 70 °C
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
BP, B port 1.62 2.3
Except B port 2
BP, B port 0.75 1.47
Except B port 0.8
AP, WIN, A port 24
BP, B port 100
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74FB2032
V
V
VOHAP, WIN, A port
V
V
V
AP, WIN, A port
V
V
V
V
BP, B
V
4.5 V
I
‡
A
I
V
I
065mA
I
(BIAS VCC)
V
V
(BIAS VCC)
V
A
9-BIT TTL/BTL COMPETITION TRANSCEIVER
SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
IK
OL
I
I
I
IH
IL
I
OZH
I
OZL
I
OZPU
I
OZPD
I
OH
I
OS
CC
C
i
C
o
C
io
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
For I/O ports, the parameters IIH and IIL include the off-state output current.
§
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
BP, B port VCC = 4.5 V, II = –18 mA –1.2
Except BP, B port VCC = 4.5 V, II = –40 mA –0.5
p
p
port
Except BP, B port VCC = 5.5 V, VI = 5.5 V 50 µA
‡
Except BP, B port VCC = 5.5 V, VI = 2.7 V 50 µA
Except BP, B port VCC = 5.5 V, VI = 0.5 V –50
BP, B port VCC = 5.5 V, VI = 0.75 V –100
AP, WIN, A port VCC = 2.1 V to 5.5 V, VO = 2.7 V 50 mA
AP, WIN, A port VCC = 2.1 V to 5.5 V, VO = 0.5 V –50 mA
AP, WIN, A port VCC = 0 V to 2.1 V, VO = 0.5 V to 2.7 V 50 mA
AP, WIN, A port VCC = 2.1 V to 0 V, VO = 0.5 V to 2.7 V –50 mA
BP, B port VCC = 0 to 5.5 V, VO = 2.1 V 100 µA
§
AP, WIN, A port VCC = 5.5 V, VO = 0 –30 –150 mA
A port to B port
B port to A port
Control Inputs VI = 0.5 V or 2.5 V 4 pF
WIN port VO = 0.5 V or 2.5 V 8 pF
A port
B port
per IEEE Std 1194.1-1991
= 4.5
CC
= 4.5
CC
=
CC
= 5.5 V,
CC
VO = 0.5 V to 2.5 V 7
VCC = 0 V to 5.5 V 5
IOH = –1 mA
IOH = –3 mA 2.5 3.3
IOL = 20 mA
IOL = 24 mA 0.35 0.5
IOL = 80 mA 0.75 1.1
IOL = 100 mA 1.15
=
O
µ
55
pF
live-insertion specifications over recommended operating free-air temperature range
6
PARAMETER TEST CONDITIONS MIN MAX UNIT
V
I
CC
O
O
B port VCC = 0, VI (BIAS VCC) = 5 V 1.62 2.1 V
B port
VCC = 0 to 4.5 V
VCC = 4.5 V to 5.5 V
VCC = 0 , VB = 1 V, VI (BIAS VCC) = 4.5 V to 5.5 V –1
VCC = 0 to 5.5 V, OEB = 0 to 0.8 V 100
VCC = 0 to 2.2 V, OEB = 0 to 5 V 100
= 0 to 2 V,
B
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I
= 4.5 V to 5.5
450
10
µ
µA
tsuSet
t
Hold ti
ns
SN74FB2032
9-BIT TTL/BTL COMPETITION TRANSCEIVER
SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
MIN MAX
t
w
h
Pulse duration LE high or low 3.3 3.3 ns
Data high before LE↑ (A to B) 1.5 1.5
up time
me
Data low before LE↑ 1.4 1.4
Data high before LE↑ (A to WIN)
Data low before LE↑
Data high before LE↑ (A to B)
Data low after LE↑ 1.3 1.3
Data high before LE↑ (A to WIN)
Data low after LE↑ 0.9 0.9
1.9 1.9
1.7 1.7
1.7 1.7
1.6 1.6
MIN MAX UNIT
ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN74FB2032
(INPUT)
(OUTPUT)
A or AP
B
BP
ns
A
B
ns
A
BP
ns
B
B
ns
LE
B
BP
ns
B
BP
A
AP
ns
B
WIN
ns
A
WIN
ns
LE
WIN
ns
COMPETE
WIN
ns
OEB
WIN
ns
COMPETE
B
ns
COMPETE
BP
ns
OEB
B
ns
OEB
B
ns
OEA
A
ns
OEA
A
ns
t
Pulse ske
ns
t
Pulse ske
ns
9-BIT TTL/BTL COMPETITION TRANSCEIVER
SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
sk(p)
sk(o)
t
r
t
f
B-port input pulse rejection 1 1 ns
Rise time, 1.3 V to 1.8 V, B outputs 1 2.2 3.2 1 3.2 ns
Fall time, 1.3 V to 1.8 V, B outputs 1 1.3 2.3 1 2.5 ns
w
w
FROM
or
A B 0.8
B A 0.5
A B 0.8
B A 0.6
TO
or
n – 1
n – 1
or
or
VCC = 5 V,
TA = 25°C
MIN TYP MAX
2.9 5.2 6.5 2.7 7
3 4.9 6.3 2.8 6.6
3.1 5.6 7.4 2.5 8.4
3.4 5.6 7.4 3.2 9
4.5 6.6 8.1 4 8.9
4.1 6.3 7.7 3.8 8.4
5.5 8.4 10.8 4.8 11.4
5.5 7.4 8.9 4.9 10
3.7 5.6 6.8 3.4 7.3
3.5 5.1 6.1 3.1 6.8
3 5.3 7 2.9 7.2
2.8 4.6 5.9 2 6.1
4 6 7.2 3.4 8.2
4.2 6.6 8.6 3.9 8.9
1.9 4.1 5.4 1.7 5.9
1.9 4 5.3 1.6 6
2.4 4.4 5.7 2.1 6.4
1.9 3.5 4.5 1.6 4.9
1.6 3.4 4.5 1.3 5
1.7 3.4 4.4 1.5 4.9
1.7 3.5 4.7 1.4 5.4
2.2 3.8 4.7 2 5
3.2 5.2 6.6 2.7 7.3
3.8 5.6 6.7 3.5 7.3
3.9 6.2 7.6 3.8 7.8
3.9 5.7 7 3.4 7.8
3.1 5.3 6.7 2.9 7.3
3.4 5.4 6.7 3.2 7.2
4.6 6.7 8.1 4.4 8.6
3.7 5.9 8.1 3.4 8.9
2.5 4.3 6 2.2 6.3
2.2 3.9 5.3 2.2 5.8
1.7 3.4 4.9 1.3 5.5
1.9 3.7 5.4 1.7 5.7
MIN MAX UNIT
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74FB2032
9-BIT TTL/BTL COMPETITION TRANSCEIVER
SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
2.1 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
1.5 V 1.5 VInput
VOLTAGE WAVEFORMS
PULSE DURATION
Input 1.5 V 1.5 V
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (A TO B)
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (B TO A)
500 Ω
500 Ω
t
w
t
PHL
t
PHL
1.5 V 1.5 V
7 V
S1
1.55 V1.55 V
1.55 V1.55 V
GND
t
PLH
t
PLH
Open
3 V
0 V
3 V
0 V
V
V
2 V
1 V
V
V
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT FOR B OUTPUTS
Timing Input
Data Input
OH
OL
OH
OL
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
ENABLE AND DISABLE TIMES (A PORT)
16.5 Ω
Test
Point
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V
t
h
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
Open
7 V
Open
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: TTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,
tf≤ 2.5 ns; BTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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