Texas Instruments SN74FB2032RC Datasheet

D

Compatible With IEEE Std 1 194.1-1991
(BTL)

D

TTL A Port, Backplane Transceiver Logic
(BTL) B Port

D

Open-Collector B-Port Outputs Sink
100 mA

D

BIAS VCC Pin Minimizes Signal Distortion
During Live Insertion or Withdrawal

9-BIT TTL/BTL COMPETITION TRANSCEIVER

D

D

D

D

RC PACKAGE

(TOP VIEW)

CC

SN74FB2032

SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999

High-Impedance State During Power Up
and Power Down

B-Port Biasing Network Preconditions the
Connector and PC Trace to the BTL
High-Level Voltage

TTL-Input Structures Incorporate Active
Clamping Networks to Aid in Line
Termination

Packaged in Plastic Quad Flatpack

GND

A3

GND

A4

GND

A5

GND

A6

GND

A7

GND

A8

GND

GND

GND

A1

WIN

CC

V

BIAS V

LE

CC

BG V

OEA

OEB

BG GND

COMPETE

A2

52 51 50 49 48 47 46 45 44 43 42 41 40

1
2
3
4
5
6
7
8
9
10
11
12
13

14 15 16 17 18 19 20 21 22 23 24 25 26

AP

OEB

TDO

TCK

TDI

V

V

CC

CC

TMS

BP

GND

GND

B1

39
38
37
36
35
34
33
32
31
30
29
28
27

B8

GND
B2
GND
B3
GND
B4
GND
B5
GND
B6
GND
B7
GND

description

The SN74FB2032 device is a 9-bit transceiver designed to translate signals between TTL and backplane
transceiver logic (BTL) environments and to perform bus arbitration. It is designed specifically to be compatible
with IEEE Std 1194.1-1991.

The B port operates at BTL-signal levels. The open-collector B ports are specified to sink 100 mA and have
minimum output edge rates of 2 ns. Two output enables (OEB and OEB) are provided for the B outputs. When
OEB is low, OEB

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

is high, or VCC is less than 2.1 V, the B port is turned off.

Copyright  1999, Texas Instruments Incorporated

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SN74FB2032
9-BIT TTL/BTL COMPETITION TRANSCEIVER

SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999

description (continued)

The A port operates at TTL-signal levels. The A outputs reflect the inverse of the data at the B port when the
A-port output enable, OEA, is high. When OEA is low or when VCC is less than 2.1 V, the A outputs are in the
high-impedance state.

The A-port data is latched when the latch enable (LE) is high. When LE is low, the latches are transparent.
The Futurebus protocol logic can be activated by taking COMPETE low. The module (device) then compares

its A data (arbitration number) against the A data of another identical module also connected to the B arbitration
bus, and sets WIN high if the A data is greater than the A data of the other module (i.e., has higher priority). A8
and B8
during this operation, and the A bus of the first module wins priority , the A bus asserts its arbitration number on
the B-arbitration bus.

AP and BP are the bus-parity bits. The winning module can assert BP low if its parity bit (AP) is high.
In a typical operating sequence, a Futurebus arbitration controller latches its arbitration number into the A port

and waits for the results of a competition. When the competition is complete, and if the controller’s arbitration
number did not win, the controller reads back the current value of the B bus (by taking OEA high) and determines
the winning arbitration number. This allows the module to change its arbitration number for the next competition
cycle, if desired.

are the most-significant bits, and A1 and B1 are the least-significant bits. If OEB is high and OEB is low

Pins are allocated for the four-wire IEEE Std 1 149.1 (JT AG) test bus. TMS and TCK are not connected and TDI
is shorted to TDO.

BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC is not connected.
BG V
The SN74FB2032 is characterized for operation from 0°C to 70°C.

and BG GND are the supply inputs for the bias generator.

CC

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION

B d

Isolation

BP

SN74FB2032

9-BIT TTL/BTL COMPETITION TRANSCEIVER

SCBS175H – NOVEMBER 1991 – REVISED SEPTEMBER 1999

Function Tables

TRANSCEIVER

INPUTS

OEA OEB OEB

L H L A data to B bus
H L X
H XH
H H L A data to B bus, B data to A bus

L L X

L X H

WIN

INPUTS

OEB

OEB COMPETE

H H X X L
H LH X L
H LLA1 < A2 L
H L L A2 ≤ A1 H

†

A1 refers to the A data of Module 1 and A2 refers to
the A data of Module 2. If LE = L, A = current A data.
If LE = H, A = the value of A8–A1 prior to the most
recent low-to-high transition of LE.

ata to A bus

DATA

†

A1, A2

WIN

BP

INPUTS

OEB OEB WIN AP

L X X X H

X HXXH
H LLXH
H LHLH

H L H H L

‡

If LE = L, AP = current AP data. If LE = H,
AP = the level of AP prior to the most
recent low-to-high transition of LE.

‡

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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