SN54F86, SN74F86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SDFS019B – JANUARY 1989 – REVISED JANUARY 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These devices contain four independent 2-input
exclusive-OR gates. They perform the Boolean
function Y = A ⊕ B or Y = A
B + AB in positive logic.
A common application is as a true/complement
element. If one of the inputs is low, the other input
is reproduced in true form at the output. If one of
the inputs is high, the signal on the other input is
reproduced inverted at the output.
The SN54F86 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F86 is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
A B
Y
L L L
L HH
HLH
HHL
logic symbol
†
1
1A
2
1B
4
2A
5
2B
9
3A
10
3B
12
4A
13
4B
1Y
3
2Y
6
3Y
8
4Y
11
= 1
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
SN54F86 ...J PACKAGE
SN74F86 ...D OR N PACKAGE
(TOP VIEW)
SN54F86 . . . FK PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3B
1Y
NC
2A
NC
2B
1B1ANC
3Y
3A
V
4B
2Y
GND
NC
CC
NC – No internal connection
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
SN54F86, SN74F86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SDFS019B – JANUARY 1989 – REVISED JANUARY 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
EXCLUSIVE OR
= 1
These are five equivalent exclusive-OR symbols valid for an ’F86 gate in positive logic; negation may be shown at any two ports.
= 2k 2k + 1
LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT ODD-PARITY ELEMENT
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of outputs
(i.e., only 1 of the 2) are
active.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current range –30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state –0.5 V to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input voltage ratings may be exceeded provided the input current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
recommended operating conditions
SN54F86 SN74F86
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
I
IK
Input clamp current –18 –18 mA
I
OH
High-level output current –1 –1 mA
I
OL
Low-level output current 20 20 mA
T
A
Operating free-air temperature –55 125 0 70 °C
SN54F86, SN74F86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SDFS019B – JANUARY 1989 – REVISED JANUARY 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54F86 SN74F86
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V, IOH = –1 mA 2.5 3.4 2.5 3.4
V
OH
VCC = 4.75 V , IOH = –1 mA 2.7
V
V
OL
VCC = 4.5 V, IOL = 20 mA 0.3 0.5 0.3 0.5 V
I
I
VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
I
IH
VCC = 5.5 V, VI = 2.7 V 20 20 µA
I
IL
VCC = 5.5 V, VI = 0.5 V –0.6 – 0.6 mA
I
OS
‡
VCC = 5.5 V, VO = 0 –60 –150 –60 –150 mA
I
CCH
VCC = 5.5 V, See Note 3 15 23 15 23 mA
I
CCL
VCC = 5.5 V, VI = 4.5 V 18 28 18 28 mA
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 3: I
CCH
is measured with outputs open, and the A or B input (not both) at 4.5 V . Remaining inputs are grounded.
switching characteristics (see Figure 1)
PARAMETER
FROM
(
INPUT
)
TO
(
OUTPUT
)
VCC = 5 V,
CL = 50 pF,
RL = 500 Ω,
TA = 25°C
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500Ω,
TA = MIN to MAX
§
UNIT
(INPUT)
(OUTPUT)
′F86 SN54F86 SN74F86
MIN TYP MAX MIN MAX MIN MAX
t
PLH
A or B
3 4 5.5 3 7 3 6.5
t
PHL
(other input low)
Y
3 4.2 5.5 2.6 8 3 6.5
ns
t
PLH
A or B
3.5 5.3 7 3.5 10 3.5 8
t
PHL
(other input high)
Y
3 4.7 6.5 3 8 3 7.5
ns
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN54F86, SN74F86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SDFS019B – JANUARY 1989 – REVISED JANUARY 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
R1
C
L
(see Note A)
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
R1
S1
7 V (t
PZL
, t
PLZ
, O.C.)
Open
(all others)
From Output
Under Test
Test
Point
R2
C
L
(see Note A)
RL = R1 = R2
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing Input
(see Note C)
Data Input
(see Note C)
1.5 V
1.5 V
3 V
3 V
0 V
0 V
High-Level
Pulse
(see Note C)
Low-Level
Pulse
t
w
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
1.5 V
t
PHL
t
PLH
t
PLH
t
PHL
Input
(see Note C)
Out-of-Phase
Output
(see Note E)
1.5 V 1.5 V
1.5 V1.5 V
1.5 V 1.5 V
3 V
0 V
V
OL
V
OH
V
OH
V
OL
In-Phase
Output
(see Note E)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
t
PHZ
t
PLZ
0.3 V
t
PZL
t
PZH
1.5 V1.5 V
1.5 V
1.5 V
3 V
0 V
Output
Control
(low-level enable)
Waveform 1
(see Notes B and E)
Waveform 2
(see Notes B and E)
0 V
V
OH
V
OL
3.5 V
0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, tr = tf≤ 2.5 ns, duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is open.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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Copyright 1998, Texas Instruments Incorporated
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