Texas Instruments JM38510-34101B2A, JM38510-34101BDA, JM38510-34101BCA, SN54F74J, SN74F74D Datasheet

SN54F74, SN74F74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR AND PRESET

SDFS046A – MARCH 1987 – REVISED OCT OBER 1993

• Package Options Include Plastic

Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs

description

These devices contain two independent positive­edge-triggered D-type flip-flops. A low level at the
preset (PRE
the outputs regardless of the levels of the other
inputs. When PRE
data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse.
Following the hold-time interval, data at the
D input may be changed without affecting the
levels at the outputs.

The SN54F74 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F74 is characterized for
operation from 0°C to 70°C.

) or clear (CLR) inputs sets or resets

and CLR are inactive (high),

SN54F74 ...J PACKAGE

SN74F74 ...D OR N PACKAGE

1CLR

1CLK
1PRE

1CLK

NC

1PRE

NC

1Q

(TOP VIEW)

14
13
12
11
10

NC

V
2CLR
2D
2CLK
2PRE
2Q

9

2Q

8

CC

V

2CLR

18
17
16
15
14

1

1D

2
3
4

1Q

5

1Q

6

GND

7

SN54F74 . . . FK PACKAGE

(TOP VIEW)

1D

1CLR

3212019

4
5
6
7
8

910111213

CC

2D
NC
2CLK
NC
2PRE

FUNCTION TABLE

INPUTS

PRE CLR CLK D Q Q

L H X X H L

H LXXLH

LLXXH
HH↑HHL
HH↑LLH
HHLXQ

†

The output levels are not guaranteed to meet the
minimum levels for VOH. Furthermore, this
configuration is nonstable; that is, it will not persist
when PRE
level.

or CLR returns to its inactive (high)

OUTPUTS

†

H

Q

0

†

0

GND

NC

2Q

1Q

NC – No internal connection

2Q

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1993, Texas Instruments Incorporated

2–1

SN54F74, SN74F74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET

SDFS046A – MARCH 1987 – REVISED OCT OBER 1993

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, and N packages.

†

1PRE

1CLK

1D

1CLR

2PRE

2CLK

2D

2CLR

4
3
2
1

10
11
12
13

S

C1
1D
R

logic diagram, each flip-flop (positive logic)

PRE

CLK

C

C

C

TG

5

1Q

6

1Q

9

2Q

8

2Q

Q

CLR

C

D

TG

C

TG

C

C

C

C

TG

C

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

Input current range –30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state –0.5 V to V

Current into any output in the low state 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range: SN54F74 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74F74 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Q

‡

CC

2–2

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SN54F74, SN74F74

UNIT

PARAMETER

TEST CONDITIONS

UNIT

V

V

I

V

V

V

mA

twPulse duration

ns

Set

CLK↑

su

thHold time, data after CLK↑

ns

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR AND PRESET

SDFS046A – MARCH 1987 – REVISED OCTOBER 1993

recommended operating conditions

SN54F74 SN74F74

MIN NOM MAX MIN NOM MAX

V

CC

V

IH

V

IL

I

IK

I

OH

I

OL

T

A

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

V

IK

OH

V

OL

I

I

I

IH

IL

I

OS

I

CC

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.

NOTE 2: ICC is measured with D, CLK, and PRE

Supply voltage 4.5 5 5.5 4.5 5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input clamp current –18 –18 mA
High-level output current –1 –1 mA
Low-level output current 20 20 mA
Operating free-air temperature –55 125 0 70 °C

SN54F74 SN74F74

MIN TYP†MAX MIN TYP†MAX

VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V, IOH = – 1 mA 2.5 3.4 2.5 3.4
VCC = 4.75 V, IOH = – 1 mA 2.7
VCC = 4.5 V, IOL = 20 mA 0.3 0.5 0.3 0.5 V
VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 20 µA

‡

Data, CLK
PRE or CLR

= 5.5 V,

CC

VCC = 5.5 V, VO = 0 –60 –150 –60 –150 mA
VCC = 5.5 V, See Note 2 10.5 16 10.5 16 mA

= 0.5

I

grounded then with D, CLK, and CLR grounded.

– 0.6 – 0.6
– 1.8 – 1.8

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

VCC = 5 V,

f

Clock frequency 0 100 0 80 0 100 MHz

clock

CLK high, PRE or CLR low 4 4 4
CLK low 5 6 5

t

su

§

Inactive-state setup time is also referred to as recovery time.

up time, data before

Setup time, inactive-state before CLK↑

High 2 3 2
Low 3 4 3

§

PRE or CLR to CLK 2 3 2
High 1 2 1
Low 1 2 1

TA = 25°C

′F74

MIN MAX MIN MAX MIN MAX

SN54F74 SN74F74

UNIT

ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2–3

SN54F74, SN74F74

(

)

(

)

(INPUT)

(OUTPUT)

CLK

Q

Q

ns

PRE or CLR

Q or Q

ns

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET

SDFS046A – MARCH 1987 – REVISED OCT OBER 1993

switching characteristics (see Note 3)

VCC = 5 V,
CL = 50 pF,

PARAMETER

f

max

t

PLH

t

PHL

t

PLH

t
†
NOTE 3: Load circuits and waveforms are shown in Section 1.

PHL

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

FROM
INPUT

TO

OUTPUT

or

RL = 500 Ω,
TA = 25°C

′F74 SN54F74 SN74F74

MIN TYP MAX MIN MAX MIN MAX

100 145 80 100 MHz

3 4.9 6.8 3.8 8.5 3 7.8

3.6 5.8 8 4.4 10.5 3.6 9.2

2.4 4.2 6.1 3.2 8 2.4 7.1

2.7 6.6 9 3.5 11.5 2.7 10.5

VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500Ω,
TA = MIN to MAX

†

UNIT

2–4

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