SN74F574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SDFS005A – D3034, SEPTEMBER 1987 – REVISED OCTOBER 1993
Copyright 1993, Texas Instruments Incorporated
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• Eight D-Type Flip-Flops in a Single
Package
• 3-State Bus-Driving True Outputs
• Full Parallel Access for Loading
• Buffered Control Inputs
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
This 8-bit flip-flop features 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. It is particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
The eight flip-flops of the SN74F574 are edge-triggered D-type flip-flops. On the positive transition of the clock
(CLK) input, the Q outputs will be set to the logic levels that were set up at the data (D) inputs.
A buffered output enable (OE
) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
The output enable (OE
) does not affect the internal operations of the flip-flops. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
The SN74F574 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE CLK D
Q
L ↑ H H
L ↑ LL
LLX Q
0
HXX Z
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
DW OR N PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74F574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SDFS005A – D3034, SEPTEMBER 1987 – REVISED OCT OBER 1993
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
logic diagram (positive logic)
OE
1D
2
1D
3
2D
4
3D
5
4D
6
5D
11
CLK
1Q
19
2Q
18
3Q
17
4Q
16
5Q
15
6Q
14
7Q
13
8Q
12
7
6D
8
7D
9
8D
EN
1
OE
CLK
1D
1Q
1
11
2
19
To Seven Other Channels
1D
C1
C1
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current range –30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the disabled or power-off state –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state –0.5 V to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input-voltage ratings may be exceeded provided the input-current ratings are observed.
recommended operating conditions
MIN NOM MAX UNIT
V
CC
Supply voltage 4.5 5 5.5 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
I
IK
Input clamp current –18 mA
I
OH
High-level output current –3 mA
I
OL
Low-level output current 24 mA
T
A
Operating free-air temperature 0 70 °C
SN74F574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SDFS005A – D3034, SEPTEMBER 1987 – REVISED OCTOBER 1993
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
VCC = 4.5 V, II = – 18 mA – 1.2 V
IOH = – 1 mA 2.5 3.4
V
OH
V
CC
=
4.5 V
IOH = – 3 mA 2.4 3.3
V
VCC = 4.75 V , IOH = – 1 mA to –3 mA 2.7
V
OL
VCC = 4.5 V, IOL = 24 mA 0.35 0.5 V
I
OZH
VCC = 5.5 V, VO = 2.7 V 50 µA
I
OZL
VCC = 5.5 V, VO = 0.5 V –50 µA
I
I
VCC = 5.5 V, VI = 7 V 0.1 mA
I
IH
VCC = 5.5 V, VI = 2.7 V 20 µA
I
IL
VCC = 5.5 V, VI = 0.5 V – 0.6 mA
I
OS
‡
VCC = 5.5 V, VO = 0 –60 – 150 mA
I
CCZ
VCC = 5.5 V, See Note 2 55 86 mA
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 2: I
CCZ
is measured with OE
at 4.5 V and all other inputs grounded.
timing requirements
VCC = 5 V,
TA = 25°C
VCC = 4.5 V to 5.5 V,
TA = MIN to MAX
§
UNIT
MIN MAX MIN MAX
f
clock
Clock frequency 0 100 0 100 MHz
CLK high 7 7
twPulse duration
CLK low 6 6
ns
Data high 2 2
t
su
Set
up time before
CLK↑
Data low 2 2
ns
Data high 2 2
t
h
Hold time after CLK↑
Data low 2 2
ns
switching characteristics (see Note 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
CL = 50 pF,
RL = 500 Ω,
TA = 25°C
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500Ω,
TA = MIN to MAX
§
UNIT
MIN TYP MAX MIN MAX
f
max
100 100 MHz
t
PLH
3.2 6.1 8.5 3.2 10
t
PHL
CLK
Any Q
3.2 6.1 8.5 3.2 10
ns
t
PZH
1.2 8.6 11.5 1.2 12.5
t
PZL
OE
Any Q
1.2 4.9 7.5 1.2 8.5
ns
t
PHZ
1.2 4.9 7 1.2 8
t
PLZ
OE
Any Q
1.2 3.9 5.5 1.2 6.5
ns
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 3: Load circuits and waveforms are shown in Section 1.
SN74F574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SDFS005A – D3034, SEPTEMBER 1987 – REVISED OCT OBER 1993
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...