Datasheet SN54F373J, SN74F373DBLE, SN74F373DBR, SN74F373DW, SN74F373DWR Datasheet (Texas Instruments)

SN54F373, SN74F373

OCTAL TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SDFS076A – D2932, MARCH 1987 – REVISED OCT OBER 1993

• Eight Latches in a Single Package

• 3-State Bus-Driving True Outputs

• Full Parallel Access for Loading

• Buffered Control Inputs

• Package Options Include Plastic

Small-Outline (SOIC) and Shrink
Small-Outline (SSOP) Packages, Ceramic
Chip Carriers, and Plastic and Ceramic
DIPs

description

These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.

The eight latches of the ′F373 are transparent
D-type latches. While the latch-enable (LE) input
is high, the Q outputs will follow the data (D) inputs.
When the latch enable is taken low, the Q outputs
are latched at the logic levels set up at the D
inputs.

A buffered output-enable (OE
to place the eight outputs in either a normal
logic state (high or low logic levels) or a
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly . The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.

) input can be used

SN54F373 ...J PACKAGE

SN74F373 ... DB, DW, OR N PACKAGE

SN54F373 . . . FK PACKAGE

2D
2Q
3Q
3D
4D

(TOP VIEW)

OE

1Q
1D
2D
2Q
3Q
3D
4D
4Q

GND

(TOP VIEW)

1D1QOE

3 2 1 20 19

4
5
6
7
8

9 10 11 12 13

4Q

1
2
3
4
5
6
7
8
9
10

GND

LE

20
19
18
17
16
15
14
13
12
11

V

CC

5Q

8Q

18
17
16
15
14

5D

V
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE

CC

8D
7D
7Q
6Q
6D

The output-enable (OE

) input does not affect the internal operations of the latches. Old data can be retained

or new data can be entered while the outputs are in the high-impedance state.
The SN74F373 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count

and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54F373 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74F373 is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

(each latch)

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

INPUTS

OE LE D

L H H H
L HL L
L LX Q

H X X Z

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OUTPUT

Q

0

Copyright  1993, Texas Instruments Incorporated

1

SN54F373, SN74F373

UNIT

OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SDFS076A – D2932, MARCH 1987 – REVISED OCT OBER 1993

1
11

3
4
7
8
13
14
17
18

†

EN
C1

1D

2
5
6

9
12
15
16
19

logic diagram (positive logic)

1

OE

11

LE

1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q

1D

3

To Seven Other Channels

C1
1D

2

1Q

logic symbol

OE
LE

1D
2D
3D
4D
5D
6D
7D
8D

†

This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

Input voltage range, VI (see Note 1) –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input current range –30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the disabled or power-off state –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state –0.5 V to V

Current into any output in the low state: SN54F373 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range: SN54F373 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74F373 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74F373 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

CC

recommended operating conditions

V

CC

V

IH

V

IL

I

IK

I

OH

I

OL

T

A

2

Supply voltage 4.5 5 5.5 4.5 5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input clamp current –18 –18 mA
High-level output current –3 –3 mA
Low-level output current 20 24 mA
Operating free-air temperature –55 125 0 70 °C

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SN54F373 SN74F373

MIN NOM MAX MIN NOM MAX

SN54F373, SN74F373

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

V

V

V

(

)

(

)

(INPUT)

(OUTPUT)

D

Q

ns

LE

Q

ns

OE

Q

ns

OE

Q

ns

OCTAL TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SDFS076A – D2932, MARCH 1987 – REVISED OCTOBER 1993

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54F373 SN74F373

MIN TYP†MAX MIN TYP†MAX

V

IK

V

OH

OL

I

OZH

I

OZL

I

I

I

IH

I

IL

‡

I

OS

I

†
‡

NOTE 2: I

CCZ

All typical values are at VCC = 5 V, TA = 25°C.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.

is measured with OE

CCZ

VCC = 4.5 V, II = –18 mA –1.2 –1.2 V

= 4.5

CC

VCC = 4.75 V, IOH = – 1 mA to –3 mA 2.7

= 4.5

CC

VCC = 5.5 V, VO = 2.7 V 50 50 µA
VCC = 5.5 V, VO = 0.5 V –50 –50 µA
VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 20 µA
VCC = 5.5 V, VI = 0.5 V – 0.6 – 0.6 mA
VCC = 5.5 V, VO = 0 –60 –150 –60 –150 mA
VCC = 5.5 V, See Note 2 38 55 38 55 mA

at 4.5 V and all other inputs grounded.

IOH = – 1 mA 2.5 3.4 2.5 3.4
IOH = – 3 mA 2.4 3.3 2.4 3.3 V

IOL = 20 mA 0.3 0.5
IOL = 24 mA 0.35 0.5

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

VCC = 5 V,

TA = 25°C

′F373

MIN MAX MIN MAX MIN MAX

t

Pulse duration, LE high 6 6 6 ns

w

t

Setup time, data before LE↓

su

t

Hold time, data after LE↓ 3 3 3 ns

h

2 2 2 ns

SN54F373 SN74F373

UNIT

switching characteristics (see Note 3)

VCC = 5 V,
CL = 50 pF,

PARAMETER

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

§
NOTE 3: Load circuits and waveforms are shown in Section 1.

PLZ

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

FROM
INPUT

TO

OUTPUT

RL = 500 Ω,
TA = 25°C

′F373 SN54F373 SN74F373

MIN TYP MAX MIN MAX MIN MAX

2.2 4.9 7 2.2 8.5 2.2 8

1.2 3.3 5 1.2 7 1.2 6

4.2 8.6 11.5 4.2 15 4.2 13

2.2 4.8 7 2.2 8.5 2.2 8

1.2 4.6 11 1.2 13.5 1.2 12

1.2 5.2 7.5 1.2 10 1.2 8.5

1.2 4.1 6.5 1.2 10 1.2 7.5

1.2 3.4 6 1.2 7 1.2 6

VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500Ω,
TA = MIN to MAX

§

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

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Copyright  1999, Texas Instruments Incorporated