SN54F32, SN74F32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDFS044B – MARCH 1987 – REVISED MA Y 1999
D
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) DIPs
description
These devices contain four independent 2-input
OR gates. They perform the Boolean functions
Y = A + B or Y = A
The SN54F32 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F32 is characterized for
operation from 0°C to 70°C.
• B in positive logic.
FUNCTION TABLE
(each gate)
INPUTS
A B
H X H
X HH
LLL
OUTPUT
Y
SN54F32 ...J PACKAGE
SN74F32 ...D OR N PACKAGE
1Y
NC
2A
NC
2B
NC – No internal connection
(TOP VIEW)
1A
1
1B
2
1Y
3
2A
4
2B
5
2Y
6
GND
SN54F32 . . . FK PACKAGE
7
(TOP VIEW)
1B1ANC
3212019
4
5
6
7
8
910111213
2Y
GND
NC
14
13
12
11
10
9
8
V
3Y
CC
4B
18
17
16
15
14
3A
V
4B
4A
4Y
3B
3A
3Y
CC
4A
NC
4Y
NC
3B
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
†
1
1A
1B
2A
2B
3A
3B
4A
4B
2
4
5
9
10
12
13
≥1
logic diagram, each gate (positive logic)
A
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3
1Y
6
2Y
8
3Y
11
4Y
Y
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54F32, SN74F32
UNIT
PARAMETER
TEST CONDITIONS
UNIT
V
V
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDFS044B – MARCH 1987 – REVISED MA Y 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
†
Input current range –30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state –0.5 V to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
Current into any output in the low state 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input voltage ratings may be exceeded provided the input current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54F32 SN74F32
MIN NOM MAX MIN NOM MAX
V
V
V
I
IK
I
OH
I
OL
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input clamp current –18 –18 mA
High-level output current –1 –1 mA
Low-level output current 20 20 mA
Operating free-air temperature –55 125 0 70 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54F32 SN74F32
MIN TYP‡MAX MIN TYP‡MAX
V
IK
OH
V
OL
I
I
I
IH
I
IL
§
I
OS
¶
I
CCH
I
‡
All typical values are at VCC = 5 V, TA = 25°C.
§
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
¶
I
CCH
CCL
is measured with one input per gate at 4.5 V and all others grounded.
VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V, IOH = –1 mA 2.5 3.4 2.5 3.4
VCC = 4.75 V, IOH = –1 mA 2.7
VCC = 4.5 V, IOL = 20 mA 0.3 0.5 0.3 0.5 V
VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 20 µA
VCC = 5.5 V, VI = 0.5 V –0.6 –0.6 mA
VCC = 5.5 V, VO = 0 –60 –150 –60 –150 mA
VCC = 5.5 V 6.1 9.2 6.1 9.2 mA
VCC = 5.5 V, VI = 0 10.3 15.5 10.3 15.5 mA
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(INPUT)
(OUTPUT)
A or B
Y
ns
SN54F32, SN74F32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDFS044B – MARCH 1987 – REVISED MA Y 1999
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
t
PLH
t
PHL
FROM
TO
VCC = 5 V,
TA = 25°C
MIN TYP MAX MIN MAX MIN MAX
2.2 3.8 5.6 2.2 7.5 2.2 6.6
2.2 3.6 5.3 1.7 7.5 2.2 6.3
SN54F32 SN74F32
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54F32, SN74F32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDFS044B – MARCH 1987 – REVISED MA Y 1999
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
C
(see Note A)
Test
Point
L
500 Ω
From Output
Under Test
(see Note A)
C
L
500 Ω
500 Ω
S1
7 V
Open
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Collector
Open
7 V
Open
7 V
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Input
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
t
w
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
VOLTAGE WAVEFORMS
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
3 V
0 V
3 V
0 V
t
PHL
V
OH
V
OL
t
PLH
V
OH
V
OL
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
t
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
h
1.5 V1.5 V
t
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
PLZ
3 V
0 V
3 V
0 V
3 V
0 V
≈ 3.5 V
V
OL
V
OH
≈ 0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns,
duty cycle = 50%.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 1999, Texas Instruments Incorporated
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