SN54F299, SN74F299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
SDFS071A – MARCH 1987 – REVISED OCTOBER 1993
• Four Modes of Operation:
Hold (Store)
Shift Right
Shift Left
Load Data
• Operates With Outputs Enabled or at High
Impedance
• 3-State Outputs Drive Bus Lines Directly
• Can Be Cascaded for N-Bit Word Lengths
• Direct Overriding Clear
• Applications:
Stacked or Push-Down Registers
Buffer Storage
SN54F299 ...J PACKAGE
SN74F299 . . . DW OR N PACKAGE
G/Q
OE1
OE2
E/Q
C/Q
A/Q
Q
CLR
GND
S0
G
E
C
A
A′
(TOP VIEW)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
V
CC
S1
SL
Q
H′
H/Q
F/Q
D/Q
B/Q
CLK
SR
H
F
D
B
Accumulator Registers
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
SN54F299 . . . FK PACKAGE
(TOP VIEW)
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These 8-bit universal shift/storage registers
feature multiplexed I/O ports to achieve full 8-bit
data handling in a single 20-pin package. Two
function-select (S0, S1) inputs and two
output-enable (OE1
choose the modes of operation listed in the
function table.
, OE2) inputs can be used to
G/Q
E/Q
C/Q
A/Q
Q
3212019
4
G
5
E
6
C
7
A
8
A′
OE2
910111213
CLR
OE1
GND
S0
SR
CC
V
CLK
S1
18
17
16
15
14
B
B/Q
SL
Q
H′
H/Q
F/Q
D/Q
H
F
D
Synchronous parallel loading is accomplished by
taking both S0 and S1 high. This places the 3-state
outputs in a high-impedance state and permits
data that is applied on the I/O ports to be clocked into the register. Reading out of the register can be
accomplished while the outputs are enabled in any mode. Clearing occurs when the clear (CLR
Taking either OE1
or OE2 high disables the outputs but has no effect on clearing, shifting, or storage of data.
) input is low.
The SN54F299 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74F299 is characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1993, Texas Instruments Incorporated
2–1
SN54F299, SN74F299
MODE
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
SDFS071A – MARCH 1987 – REVISED OCT OBER 1993
FUNCTION TABLE
INPUTS I/O PORTS OUTPUTS
CLR S1 S0 OE1†OE2†CLK SL SR A/QAB/QBC/QCD/QDE/QEF/QFG/QGH/QHQA′Q
L
X
L
L
L
L
X
Clear
L
H
Hold
Shift
RightHHLLHH
Shift
LeftHHHHLL
Load H H H X X ↑ X X a b c d e f g h a h
NOTE: a ...h = the level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flip-flop outputs
†
When one or both output-enable inputs are high the eight I/O terminals are disabled to the high-impedance state; however, sequential operation
or clearing of the register is not affected.
HHLXL
are isolated from the I/O terminals.
L
H
X
L
X
L
L
L
L
L
L
X
X
L
X
X
X
X
X
L
XLXXXXQ
L
L
↑↑XXHLHLQ
L
L
↑↑HLXXQ
L
X
L
L
L
L
L
L
L
L
X
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
Q
Q
Q
Q
Q
Q
Q
A0
B0
C0
D0
E0
F0
Q
Q
Q
Q
Q
A0
B0
C0
D0
Q
An
Q
An
Q
Bn
Bn
Cn
Q
Cn
Q
Q
Bn
Bn
Dn
Dn
Cn
Q
Cn
Q
En
Q
En
Q
Q
Q
Q
E0
Q
Q
Dn
Q
Q
Dn
Q
Q
Fn
Q
Q
Fn
F0
En
En
Gn
Gn
G0
Q
G0
Q
Fn
Q
Fn
Q
Hn
Q
Hn
H0
Q
H0
Q
Gn
Q
Gn
HLQ
Q
Q
Q
L
L
L
A0
A0
HLQ
Bn
Bn
H′
L
L
L
Q
H0
Q
H0
Gn
Q
Gn
H
L
logic symbol
‡
CLR
OE1
OE2
CLK
A/Q
B/Q
C/Q
D/Q
E/Q
F/Q
G/Q
H/Q
S0
S1
SR
SL
9
2
3
1
19
12
11
7
A
13
B
6
C
14
D
5
E
15
F
4
G
16
H
18
R
&
0
M
1
C4/1→/2→
1,4D
3,4D
5
3,4D
5
3,4D
5
2,4D
SRG8
3
EN5
0
3
17
8
Q
A′
Q
H′
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
S0
19
S1
11
SR
(shift right
serial input)
12
CLK
SN54F299, SN74F299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
SDFS071A – MARCH 1987 – REVISED OCTOBER 1993
18
SL
(shift left
serial input)
Six
Identical
Channels
Not
†
Shown
1D
C1
RR
8
Q
A′
9
CLR
2
OE1
3
OE2
†
I/O ports not shown: B/QB (13), C/QC (6), D/QD (14), E/QE (5), F/QF (15), and G/QG (4).
716
A/Q
A
H/Q
1D
C1
17
Q
H′
H
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Input current range –30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the disabled or power-off state –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state –0.5 V to V
Current into any output in the low state: Q
Operating free-air temperature range: SN54F299 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
or QH′ 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A′
SN54F299 (Q
SN74F299 (Q
thru QH) 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
thru QH) 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
SN74F299 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
CC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–3
SN54F299, SN74F299
UNIT
IOHHigh-level output current
mA
IOLLow-level output current
mA
PARAMETER
TEST CONDITIONS
UNIT
VOHQ
thru Q
V
Q
thru Q
I
V
V
mA
I
‡
V
V
V
A
‡
IL
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
SDFS071A – MARCH 1987 – REVISED OCT OBER 1993
recommended operating conditions
SN54F299 SN74F299
MIN NOM MAX MIN NOM MAX
V
CC
V
IH
V
IL
I
IK
T
A
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
V
IK
V
OL
I
IH
I
IL
I
OS
I
CC
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
For I/O ports (QA thru QH), the parameters IIH and IIL include the off-state output current.
§
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 2: ICC is measured with OE1
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input clamp current –18 –18 mA
p
p
Operating free-air temperature –55 125 0 70 °C
VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
QA′ or Q
Any output VCC = 4.75 V, IOH = – 1 mA to –3 mA 2.7
QA′ or Q
A thru H
Any other
A thru H
Any other
A thru H –0.65 –0.65
S0 or S1
Any other –0.6 –0.6
§
H′
A
A
VCC = 4.5 V
H
H′
VCC = 4.5 V
H
= 5.5
CC
= 5.5 V,
CC
VCC = 5.5 V, VI = 0.5 V
VCC = 5.5 V, VO = 0 –60 –150 –60 –150 mA
VCC = 5.5 V, See Note 2 68 95 68 95 mA
, OE2, and CLK at 4.5 V.
QA′ or Q
QA thru Q
QA′ or Q
QA thru Q
IOH = – 1 mA 2.5 3.4 2.5 3.4
IOH = – 1 mA 2.5 3.4 2.5 3.4
IOH = – 3 mA 2.4 3.3 2.4 3.3
IOL = 20 mA 0.3 0.5 0.3 0.5
IOL = 20 mA 0.3 0.5
IOL = 24 mA 0.35 0.5
VI = 5.5 V 1 1
VI = 7 V 0.1 0.1
= 2.7
I
H′
H
H′
H
SN54F299 SN74F299
MIN TYP†MAX MIN TYP†MAX
–1 –1
–3 –3
20 20
20 24
70 70
20 20
–1.2 –1.2
V
µ
mA
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54F299, SN74F299
twPulse duration
ns
Setu time before
t
ns
t
Hold ti
CLK↑
ns
(INPUT)
(OUTPUT)
CLK
Q
Q
ns
CLK
Q
Q
ns
t
CLR
ns
OE1
OE2
Q
Q
ns
OE1 or OE2
Q
thru Q
ns
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
SDFS071A – MARCH 1987 – REVISED OCTOBER 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25°C
′F299
MIN MAX MIN MAX MIN MAX
f
clock
su
h
†
Inactive-state setup time is also referred to as recovery time.
Clock frequency 0 70 0 65 0 70 MHz
CLK high or low 7 8 7
CLR low 7 8 7
Setup time before
CLK↑
Inactive-state setup
time before CLK↑
me after
S0 or S1 High or low 8.5 9.5 8.5
A/QA thru H/QH, SR, or SL
CLR High 7 13 7
†
S0 or S1 High or low 0 0 0
A/QA thru H/QH, SR, or SL
High or low 5.5 6.5 5.5
High or low 2 2 2
switching characteristics (see Note 3)
VCC = 5 V,
CL = 50 pF,
PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
PHL
t
PZH
t
PZL
t
PHZ
t
‡
NOTE 3: Load circuits and waveforms are shown in Section 1.
PLZ
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
FROM
or
TO
or
A′
thru
A
QA′ or Q
QA thru Q
thru
A
A
H′
H
H′
H
H
H
RL = 500 Ω,
TA = 25°C
′F299 SN54F299 SN74F299
MIN TYP MAX MIN MAX MIN MAX
70 100 65 70 MHz
3.2 6.6 9 2.7 10.5 3.2 10
2.7 6.1 8.5 2.2 10 2.7 9.5
3.2 6.6 9 2.7 11 3.2 10
4.2 8.1 11 3.7 12.5 4.2 12
3.7 7.1 9.5 3.2 11.5 3.7 10.5
5.7 10.6 14 5 15.5 5.7 15
2.7 5.6 8 2.2 10.5 2.7 9
3.2 6.6 10 2.7 12 3.2 11
1.7 4.1 6 1.7 9 1.7 7
1.2 3.6 5.5 1.2 7.5 1.2 6.5
SN54F299 SN74F299
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500Ω,
TA = MIN to MAX
‡
UNIT
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–5
SN54F299, SN74F299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
SDFS071A – MARCH 1987 – REVISED OCT OBER 1993
2–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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