Texas Instruments SN74F2373DBLE, SN74F2373DBR, SN74F2373DW, SN74F2373DWR, SN74F2373N Datasheet
SN74F2373
25-Ω OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDFS100 – JANUARY 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Eight Latches in a Single Package
D
3-State True Outputs With 25-Ω Sink
Resistors
D
Full Parallel Access for Loading
D
Buffered Control Inputs
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB) Packages, and Plastic (N) DIPs
description
This 8-bit latch features 3-state outputs designed
to sink up to 12 mA, and include 25-Ω sink resitors
to reduce overshoot and undershoot.
The eight latches of the SN74F2373 are transparent D-type latches. While the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When the LE is taken low, the Q outputs are latched at the logic levels
set up at the D inputs.
A buffered output-enable (OE
) input can be used to place the eight outputs in either a normal
logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither
load nor drive the bus lines significantly . The high-impedance state and increased drive provide the capability
to drive bus lines without need for interface or pullup components.
OE
input does not affect the internal operations of the latches. Old data can be retained or new data can be
entered while the outputs are in the high-impedance state.
The SN74F373 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN74F373 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
OE LE D
Q
L H H H
L HL L
LLX Q
0
HXX Z
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
DB, DW, OR N PACKAGE
(TOP VIEW)
SN74F2373
25-Ω OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDFS100 – JANUARY 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
logic diagram (positive logic)
OE
1D
3
1D
4
2D
7
3D
8
4D
13
5D
C1
11
LE
1Q
2
2Q
5
3Q
6
4Q
9
5Q
12
6Q
15
7Q
16
8Q
19
14
6D
17
7D
18
8D
EN
1
OE
LE
1D
1Q
1
11
3
2
To Seven Other Channels
C1
1D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
schematic diagram
Q
V
CC
25 Ω
(nominal)
Typical Output Configuration
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