Texas Instruments SN74F2373DBLE, SN74F2373DBR, SN74F2373DW, SN74F2373DWR, SN74F2373N Datasheet

SN74F2373

25-Ω OCTAL TRANSPARENT D-TYPE LATCH

WITH 3-STATE OUTPUTS

SDFS100 – JANUARY 1996

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Eight Latches in a Single Package

D

3-State True Outputs With 25-Ω Sink
Resistors

D

Full Parallel Access for Loading

D

Buffered Control Inputs

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB) Packages, and Plastic (N) DIPs

description

This 8-bit latch features 3-state outputs designed
to sink up to 12 mA, and include 25-Ω sink resitors
to reduce overshoot and undershoot.

The eight latches of the SN74F2373 are transparent D-type latches. While the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When the LE is taken low, the Q outputs are latched at the logic levels
set up at the D inputs.

A buffered output-enable (OE

) input can be used to place the eight outputs in either a normal
logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither
load nor drive the bus lines significantly . The high-impedance state and increased drive provide the capability
to drive bus lines without need for interface or pullup components.

OE

input does not affect the internal operations of the latches. Old data can be retained or new data can be

entered while the outputs are in the high-impedance state.
The SN74F373 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count

and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN74F373 is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

(each latch)

INPUTS

OUTPUT

OE LE D

Q

L H H H
L HL L
LLX Q

0

HXX Z

Copyright  1996, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

OE

1Q
1D
2D
2Q
3Q
3D
4D
4Q

GND

V

CC

8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE

DB, DW, OR N PACKAGE

(TOP VIEW)

SN74F2373
25-Ω OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS

SDFS100 – JANUARY 1996

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

logic diagram (positive logic)

OE

1D

3

1D

4

2D

7

3D

8

4D

13

5D

C1

11

LE

1Q

2

2Q

5

3Q

6

4Q

9

5Q

12

6Q

15

7Q

16

8Q

19

14

6D

17

7D

18

8D

EN

1

OE

LE

1D

1Q

1

11

3

2

To Seven Other Channels

C1
1D

†

This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.

schematic diagram

Q

V

CC

25 Ω
(nominal)

Typical Output Configuration

SN74F2373

25-Ω OCTAL TRANSPARENT D-TYPE LATCH

WITH 3-STATE OUTPUTS

SDFS100 – JANUARY 1996

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(see Note 1) –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input current range, I

I

–30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the disabled or power-off state, V

O

–0.5 V to 5.5 V. . . . . . . . . . . . . . .

Voltage range applied to any output in the high state, V

O

–0.5 V to V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the low state, I

O

30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range,T

A

0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The input voltage ratings may be exceeded if the input current ratings are observed.

recommended operating conditions

MIN NOM MAX UNIT

V

CC

Supply voltage 4.5 5 5.5 V

V

IH

High-level input voltage 2 V

V

IL

Low-level input voltage 0.8 V

I

IK

Input clamp current –18 mA

I

OH

High-level output current –3 mA

I

OL

Low-level output current 12 mA

T

A

Operating free-air temperature 0 70 °C

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

V

IK

VCC = 4.5 V, II = –18 mA –1.2 V

IOH = – 1 mA 2.5 3.4

V

OH

V

CC

= 4.5

V

IOH = – 3 mA 2.4 3.3

V

VCC = 4.75 V , IOH = -1 mA to – 3 mA 2.7

IOL = 1 mA 0.2 0.5

V

OL

V

CC

= 4.5

V

IOL = 12 mA 0.5 0.75

V

I

OZ(H)

VCC = 5.5 V, VO = 2.7 V 50 µA

I

OZ(L)

VCC = 5.5 V, VO = 0.5 V –50 µA

I

I

VCC = 5.5 V, VI = 7 V 0.1 mA

I

IH

VCC = 5.5 V, VI = 2.7 V 20 µA

I

IL

VCC = 5.5 V, VI = 0.5 V – 0.6 mA

I

OS

§

VCC = 5.5 V, VO = 0 –60 –150 mA

I

CC(H)

VCC = 5.5 V, See Note 2, Condition A 38 55 mA

I

CC(L)

VCC = 5.5 V, See Note 2, Condition B 46 66 mA

I

CC(Z)

VCC = 5.5 V, See Note 2, Condition C 43 62 mA

‡

All typical values are at VCC = 5 V, TA = 25°C.

§

Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.

NOTE 2: ICC is measured with the outputs open under the following conditions:

A. OE

at ground (0) and all other inputs at 4.5 V .
B. LE at 4.5 V and all other inputs grounded.
C. OE

at 4.5 V and all other inputs grounded.

SN74F2373
25-Ω OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS

SDFS100 – JANUARY 1996

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

VCC = 5 V,

TA = 25°C

MIN MAX UNIT

MIN MAX

t

w

Pulse duration, LE high 6 6 ns

t

su

Setup time, data before LE↓

2 2 ns

t

h

Hold time, data after LE↓ 5 6 ns

switching characteristics (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,
CL = 50 PF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = 25°C

VCC = 4.5 V TO 5.5 V, C

L

= 50 PF,
R1 = 500Ω,
R2 = 500Ω,
TA = MIN TO MAX

†

UNIT

MIN TYP MAX MIN MAX

t

PLH

2.2 4.4 7 2.1 9

t

PHL

D

Q

1.2 4.1 5.5 1.2 7

ns

t

PLH

4.2 7.3 11.5 4.2 13

t

PHL

LE

Q

2.2 4.2 7 2.2 8

ns

t

PZH

1.2 4.1 11 1.2 12

t

PZL

OE

Q

1.2 6 8.3 1.2 9.5

ns

t

PHZ

1.2 4.2 6.5 1.2 7.5

t

PLZ

OE

Q

1.2 3.5 6 1.2 6

ns

†

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

SN74F2373

25-Ω OCTAL TRANSPARENT D-TYPE LATCH

WITH 3-STATE OUTPUTS

SDFS100 – JANUARY 1996

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

Test
Point

R1

C

L

(see Note A)

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

LOAD CIRCUIT FOR

3-STATE AND OPEN-COLLECTOR OUTPUTS

R1

S1

7 V (t

PZL

, t

PLZ

, O.C.)

Open
(all others)

From Output

Under Test

Test
Point

R2

C

L

(see Note A)

RL = R1 = R2

1.5 V

1.5 V

1.5 V

3 V

3 V

0 V

0 V

t

h

t

su

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Timing Input

(see Note C)

Data Input

(see Note C)

1.5 V

1.5 V

3 V

3 V

0 V

0 V

High-Level

Pulse

(see Note C)

Low-Level

Pulse

t

w

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V

1.5 V

t

PHL

t

PLH

t

PLH

t

PHL

Input

(see Note C)

Out-of-Phase

Output

(see Note E)

1.5 V 1.5 V

1.5 V1.5 V

1.5 V 1.5 V

3 V

0 V

V

OL

V

OH

V

OL

In-Phase

Output

(see Note E)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (see Note D)

t

PHZ

t

PLZ

0.3 V

t

PZL

t

PZH

1.5 V1.5 V

1.5 V

3 V

0 V

Output

Control

(low-level enable)

Waveform 2

(see Notes B and E)

0 V

V

OH

V

OL

3.5 V

0.3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

Waveform 1

(see Notes B and E)

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, tr = tf≤ 2.5 ns, duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is open.
E. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

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