Texas Instruments SN74F175D, SN74F175DR, SN74F175N, SN74F175N3 Datasheet
SN54F175, SN74F175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SDFS058A – D2932, MARCH 1987 – REVISED OCT OBER 1993
• Contain Four Flip-Flops With Double-Rail
Outputs
• Buffered Clock and Direct Clear Inputs
• Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These monolithic, positive-edge-triggered flipflops utilize TTL circuitry to implement D-type
flip-flop logic with a direct clear (CLR
Information at the data (D) inputs meeting setup
time requirements is transferred to outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a particular voltage level and
is not directly related to the transition time of the
positive-going pulse. When the clock (CLK) input
is at either the high or low level, the D-input signal
has no effect at the output.
) input.
SN54F175 ...J PACKAGE
SN74F175 ...D OR N PACKAGE
1Q
1D
NC
2D
2Q
(TOP VIEW)
1
16
15
14
13
12
11
10
NC
V
CC
4Q
4Q
4D
3D
3Q
3Q
9
CLK
CC
V
4Q
18
17
16
15
14
CLR
2
1Q
3
1Q
4
1D
5
2D
6
2Q
7
2Q
GND
SN54F175 . . . FK PACKAGE
8
(TOP VIEW)
1Q
CLR
3212019
4
5
6
7
8
910111213
4Q
4D
NC
3D
3Q
The SN54F175 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F175 is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
CLR CLK D Q Q
L X X L H
H ↑ HHL
H↑LLH
HLXQ
OUTPUTS
Q
0
2Q
GND
NC – No internal connection
0
NC
CLK
3Q
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1993, Texas Instruments Incorporated
2–1
SN54F175, SN74F175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SDFS058A – D2932, MARCH 1987 – REVISED OCT OBER 1993
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
CLR
CLK
1D
2D
3D
4D
1
9
4
5
12
13
R
C1
1D
logic diagram (positive logic)
1D
1
9
4
1D
C1
R
CLR
CLK
10
11
15
14
2
1Q
3
1Q
7
2Q
6
2Q
3Q
3Q
4Q
4Q
2
1Q
3
1Q
13
4D
Pin numbers shown are for the D, J, and N packages.
Two Identical Channels
Not Shown
1D
C1
R
15
14
4Q
4Q
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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