SN54F175, SN74F175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SDFS058A – D2932, MARCH 1987 – REVISED OCT OBER 1993
• Contain Four Flip-Flops With Double-Rail
Outputs
• Buffered Clock and Direct Clear Inputs
• Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These monolithic, positive-edge-triggered flipflops utilize TTL circuitry to implement D-type
flip-flop logic with a direct clear (CLR
Information at the data (D) inputs meeting setup
time requirements is transferred to outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a particular voltage level and
is not directly related to the transition time of the
positive-going pulse. When the clock (CLK) input
is at either the high or low level, the D-input signal
has no effect at the output.
) input.
SN54F175 ...J PACKAGE
SN74F175 ...D OR N PACKAGE
1Q
1D
NC
2D
2Q
(TOP VIEW)
1
16
15
14
13
12
11
10
NC
V
CC
4Q
4Q
4D
3D
3Q
3Q
9
CLK
CC
V
4Q
18
17
16
15
14
CLR
2
1Q
3
1Q
4
1D
5
2D
6
2Q
7
2Q
GND
SN54F175 . . . FK PACKAGE
8
(TOP VIEW)
1Q
CLR
3212019
4
5
6
7
8
910111213
4Q
4D
NC
3D
3Q
The SN54F175 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F175 is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
CLR CLK D Q Q
L X X L H
H ↑ HHL
H↑LLH
HLXQ
OUTPUTS
Q
0
2Q
GND
NC – No internal connection
0
NC
CLK
3Q
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1993, Texas Instruments Incorporated
2–1
SN54F175, SN74F175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SDFS058A – D2932, MARCH 1987 – REVISED OCT OBER 1993
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
CLR
CLK
1D
2D
3D
4D
1
9
4
5
12
13
R
C1
1D
logic diagram (positive logic)
1D
1
9
4
1D
C1
R
CLR
CLK
10
11
15
14
2
1Q
3
1Q
7
2Q
6
2Q
3Q
3Q
4Q
4Q
2
1Q
3
1Q
13
4D
Pin numbers shown are for the D, J, and N packages.
Two Identical Channels
Not Shown
1D
C1
R
15
14
4Q
4Q
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54F175, SN74F175
UNIT
PARAMETER
TEST CONDITIONS
UNIT
V
V
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SDFS058A – D2932, MARCH 1987 – REVISED OCTOBER 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Input current range –30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state –0.5 V to V
Current into any output in the low state 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54F175 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74F175 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
SN54F175 SN74F175
MIN NOM MAX MIN NOM MAX
V
V
V
I
I
I
T
CC
IH
IL
IK
OH
OL
A
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input clamp current –18 –18 mA
High-level output current –1 –1 mA
Low-level output current 20 20 mA
Operating free-air temperature –55 125 0 70 °C
†
CC
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54F175 SN74F175
MIN TYP‡MAX MIN TYP‡MAX
V
IK
OH
V
OL
I
I
I
IH
I
IL
§
I
OS
I
‡
§
NOTE 2: ICC is measured with outputs open with 4.5 V applied to all data inputs after a momentary ground followed by 4.5 V applied to CLK.
CC
All typical values are at VCC = 5 V, TA = 25°C.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V, IOH = – 1 mA 2.5 3.4 2.5 3.4
VCC = 4.75 V, IOH = – 1 mA 2.7
VCC = 4.5 V, IOL = 20 mA 0.3 0.5 0.3 0.5 V
VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 20 µA
VCC = 5.5 V, VI = 0.5 V – 0.6 – 0.6 mA
VCC = 5.5 V, VO = 0 –60 –150 –60 –150 mA
VCC = 5.5 V, See Note 2 22.5 34 22.5 34 mA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–3
SN54F175, SN74F175
t
ns
(
)
(
)
(INPUT)
(OUTPUT)
CLK
Q
Q
ns
CLR
ns
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SDFS058A – D2932, MARCH 1987 – REVISED OCT OBER 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25°C
′F175
MIN MAX MIN MAX MIN MAX
f
Clock frequency 0 100 0 100 0 100 MHz
clock
CLK high 4 4 4
t
Pulse duration
w
Setup time, data before CLK↑
su
Setup time, inactive state, data before CLK↑
t
Hold time, data after CLK↑ High or low 1 1 1 ns
h
†
Inactive-state setup time is also referred to as recovery time.
CLK low 5 5 5
CLR low 5 5 5
High or low 3 3 3
†
CLR high 5 5 5
switching characteristics (see Note 3)
VCC = 5 V,
CL = 50 pF,
PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 3: Load circuits and waveforms are shown in Section 1.
FROM
INPUT
TO
OUTPUT
or
Q
Q
RL = 500 Ω,
TA = 25°C
′F175 SN54F175 SN74F175
MIN TYP MAX MIN MAX MIN MAX
100 140 100 100 MHz
3.2 4.6 6.5 2.7 8.5 3.2 7.5
3.2 6.1 8.5 3.2 10.5 3.2 9.5
3.2 6.1 8.5 3.2 10 3.2 9
3.7 8.6 11.5 3.7 15 3.7 13
SN54F175 SN74F175
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500Ω,
TA = MIN to MAX
‡
UNIT
ns
UNIT
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...