SN74F174A
HEX D-TYPE FLIP-FLOP
WITH CLEAR
SDFS029B – D2932, MARCH 1987 – REVISED OCTOBER 1993
Copyright 1993, Texas Instruments Incorporated
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• Contains Six Flip-Flops With Single-Rail
Outputs
• Buffered Clock and Direct Clear Inputs
• Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
• Fully Buffered Outputs for Maximum
Isolation From External Disturbances
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
This monolithic, positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a
direct clear (CLR
) input. Information at the data (D) inputs meeting the setup time requirements is transferred
to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level
and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either
the high or low level, the D-input signal has no effect at the output.
The SN74F174A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
CLR CLK D
Q
H L X Q
0
H ↑ HH
H↑LL
LXXL
logic symbol
†
1D
3
1D
4
2D
6
3D
11
4D
13
5D
1Q
2
2Q
5
3Q
7
4Q
10
5Q
12
R
1
9
CLK
CLR
C1
14
6D
6Q
15
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
1Q
1D
2D
2Q
3D
3Q
GND
V
CC
6Q
6D
5D
5Q
4D
4Q
CLK
D OR N PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74F174A
HEX D-TYPE FLIP-FLOP
WITH CLEAR
SDFS029B – D2932, MARCH 1987 – REVISED OCTOBER 1993
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
15
6Q
14
1Q
3
1
9
C1
1D
2
C1
1D
CLR
CLK
1D
6D
R
R
Four Identical Channels
Not Shown
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current range –30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to any output in the high state –0.5 V to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input-voltage ratings may be exceeded provided the input-current ratings are observed.
recommended operating conditions
MIN NOM MAX UNIT
V
CC
Supply voltage 4.5 5 5.5 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
I
IK
Input clamp current –18 mA
I
OH
High-level output current –1 mA
I
OL
Low-level output current 20 mA
T
A
Operating free-air temperature 0 70 °C
SN74F174A
HEX D-TYPE FLIP-FLOP
WITH CLEAR
SDFS029B – D2932, MARCH 1987 – REVISED OCTOBER 1993
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
VCC = 4.5 V, II = – 18 mA – 1.2 V
VCC = 4.5 V, IOH = – 1 mA 2.5 3.4
V
OH
VCC = 4.75 V , IOH = – 1 mA 2.7
V
V
OL
VCC = 4.5 V, IOL = 20 mA 0.3 0.5 V
I
I
VCC = 5.5 V, VI = 7 V 0.1 mA
I
IH
VCC = 5.5 V, VI = 2.7 V 20 µA
I
IL
VCC = 5.5 V, VI = 0.5 V – 0.6 mA
I
OS
‡
VCC = 5.5 V, VO = 0 –60 – 150 mA
I
CCH
VCC = 5.5 V, See Note 2 30 45 mA
I
CCL
VCC = 5.5 V, See Note 3 39 55 mA
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTES: 2. I
CCH
is measured with all outputs open, all data inputs and enable input at 4.5 V , and the clock input at 4.5 V after being momentarily
grounded.
3. I
CCL
is measured with all outputs open, all data inputs and enable input at 0 V , and the clock input at 4.5 V after being momentarily
grounded.
timing requirements
VCC = 5 V,
TA = 25°C
VCC = 4.5 V to 5.5 V,
TA = MIN to MAX
§
UNIT
MIN MAX MIN MAX
f
clock
Clock frequency 0 100 0 80 MHz
CLK high 4 4
t
w
Pulse duration CLK low 6 6 ns
CLR low 5 5
Data high or low 4.5 4.5
t
su
Set
up time before
CLK↑
CLR high¶ 5 5
ns
t
h
Hold time after CLK↑ Data high or low 0.5 1 ns
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
¶
Inactive-state setup time is also referred to as recovery time.
switching characteristics (see Note 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
CL = 50 pF,
RL = 500 Ω,
TA = 25°C
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500Ω,
TA = MIN to MAX
§
UNIT
MIN TYP MAX MIN MAX
f
max
100 140 80 MHz
t
PLH
2.7 4.5 8 2.7 9
t
PHL
CLK
Any Q
3.4 4.2 10 3.3 11
ns
t
PHL
CLR Any Q 4.2 6.3 14 4.2 15 ns
NOTE 4: Load circuits and waveforms are shown in Section 1.
SN74F174A
HEX D-TYPE FLIP-FLOP
WITH CLEAR
SDFS029B – D2932, MARCH 1987 – REVISED OCTOBER 1993
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated
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