SN74F169
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SDFS089 – MARCH 1987 – REVISED OCTOBER 1993
Copyright 1993, Texas Instruments Incorporated
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• Fully Synchronous Operation for Counting
and Programming
• Internal Look-Ahead Circuitry for Fast
Counting
• Carry Output for N-Bit Cascading
• Fully Independent Clock Circuit
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
This synchronous, presettable, 4-bit up/down binary counter features an internal carry look-ahead circuitry for
cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops
clocked simultaneously so that the outputs change coincident with each other when so instructed by the
count-enable (ENP
, ENT) inputs and internal gating. This mode of operation eliminates the output counting
spikes that are normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input
triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.
This counter is fully programmable; that is, it may be preset to any number between 0 and its maximum count.
The load-input circuitry allows loading with the carry-enable output of cascaded counters. As loading is
synchronous, setting up a low level at the load (LOAD
) input disables the counter and causes the outputs to
agree with the data inputs after the next clock pulse.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous application without
additional gating. Instrumental in accomplishing this function are two count-enable (ENP
, ENT) inputs and a
ripple-carry (RCO
) output. Both ENP and ENT must be low to count. The direction of the count is determined
by the level of the up/down (U/D
) input. When U/D is high, the counter counts up; when low, it counts down. Input
ENT
is fed forward to enable the RCO. RCO thus enabled will produce a low-level pulse while the count is zero
(all inputs low) counting down or maximum (9 or 15) counting up. This low-level overflow ripple-carry pulse can
be used to enable successive cascaded stages. Transitions at ENP
or ENT are allowed regardless of the level
of the clock input. All inputs are diode clamped to minimize transmission-line effects, thereby simplifying system
design.
The SN74F169 features a fully independent clock circuit. Changes at control inputs (ENP
, ENT, LOAD or U/D)
that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The
function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions
meeting the setup and hold times.
The SN74F169 is characterized for operation from 0°C to 70°C.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
U/D
CLK
A
B
C
D
ENP
GND
V
CC
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
D OR N PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74F169
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SDFS089 – MARCH 1987 – REVISED OCTOBER 1993
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
CTRDIV16
LOAD
1, 7D
3
A
4
B
5
C
6
D
M2 [COUNT]
M1 [LOAD]
9
2,3,5,6+/C7
G5
10
15
3,5CT = 15
14
13
12
11
Q
A
Q
B
Q
C
Q
D
G6
7
2
CLK
1
2
4
8
U/D
M4 [DOWN]
M3 [UP]
1
2,4,5,6 –
ENT
ENP
RCO
4,5CT = 0
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN74F169
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SDFS089 – MARCH 1987 – REVISED OCTOBER 1993
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
G2
1
, 2T/C3
1, 3D
M1
9
1
10
7
2
3
15
14
LOAD
U/D
ENT
ENP
CLK
A
RCO
Q
A
G2
1
, 2T/C3
1, 3D
M1
4
13
B
Q
B
G2
1
, 2T/C3
1, 3D
M1
5
12
C
Q
C
G2
1
, 2T/C3
1, 3D
M1
6
11
D
Q
D
SN74F169
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SDFS089 – MARCH 1987 – REVISED OCTOBER 1993
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol, each flip-flop
G2TE
Q2
1, 3DDATA
M1LOAD
Q1
1, 2T/C3
CLK
Q1
Q
2
logic diagram, each flip-flop (positive logic)
TE
(Toggle
Enable)
CLK
DATA
LOAD
Q1
Q2
Q
1
Q
2
FUNCTION TABLE
(each flip-flop)
COUNTER
INPUTS
FLIP-FLOP INPUTS OUTPUTS
LOAD CLK LOAD TE CLK DATA Q Q
L ↑ H L ↓ H H L
L ↑ H L ↓ LLH
H↑LH↓XQ
0
Q
0
H ↑ L L ↓ XQ
0
Q
0
SN74F169
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SDFS089 – MARCH 1987 – REVISED OCTOBER 1993
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical load, count, and inhibit sequences
Illustrated below is the following sequence:
1. Load (preset) to binary thirteen
2. Count up to fourteen, fifteen (maximum), zero, one, and two
3. Inhibit
4. Count down to one, zero (minimum), fifteen, fourteen, and thirteen
Data
Inputs
Data
Outputs
LOAD
A
B
C
D
CLK
U/D
ENP and ENT
RCO
Q
A
Q
B
Q
C
Q
D
Load
Count Up Inhibit
13 14
15 0 012
Count Down
221 1315 14
SN74F169
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SDFS089 – MARCH 1987 – REVISED OCTOBER 1993
2–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current range –30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state –0.5 V to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
recommended operating conditions
MIN NOM MAX UNIT
V
CC
Supply voltage 4.5 5 5.5 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
I
IK
Input clamp current –18 mA
I
OH
High-level output current –1 mA
I
OL
Low-level output current 20 mA
T
A
Operating free-air temperature 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 V
VCC = 4.5 V, IOH = – 1 mA 2.5 3.4
V
OH
VCC = 4.75 V , IOH = – 1 mA 2.7
V
V
OL
VCC = 4.5 V, IOL = 20 mA 0.3 0.5 V
I
I
VCC = 5.5 V, VI = 7 V 0.1 mA
I
IH
VCC = 5.5 V, VI = 2.7 V 20 µA
ENT
– 1.2
I
IL
All others
V
CC
= 5.5 V,
V
I
= 0.5
V
– 0.6
mA
I
OS
§
VCC = 5.5 V, VO = 0 –60 –150 mA
I
CC
VCC = 5.5 V, See Note 2 38 52 mA
‡
All typical values are at VCC = 5 V, TA = 25°C.
§
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 2: ICC is measured after applying a momentary 4.5 V , then ground, to the clock input with B and ENT
inputs high and all other inputs low.
SN74F169
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SDFS089 – MARCH 1987 – REVISED OCTOBER 1993
2–7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25°C
MIN MAX UNIT
MIN MAX
f
clock
Clock frequency 0 100 0 90 MHz
t
w
Pulse duration CLK high or low 5 5.5 ns
Data before CLK↑ High or low 4 4.5
LOAD before CLK↑
High or low 8 9
t
su
Setup time
ENP
and ENT before CLK↑ High or low 5 6
ns
High 11 12.5
U/D bef
ore
CLK↑
Low 7 8
Data after CLK↑ High or low 3 3.5
LOAD after CLK↑
High or low 0 0
thHold time
ENP and ENT after CLK↑ High or low 0 0
ns
U/D after CLK↑ High or low 0 0
switching characteristics (see Note 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
CL = 50 pF,
RL = 500 Ω,
TA = 25°C
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500Ω,
TA = MIN to MAX
†
UNIT
MIN TYP MAX MIN MAX
f
max
100 115 90 MHz
t
PLH
2.2 6.1 8.5 2.2 9.5
t
PHL
CLK
Q
3.2 8.6 11.5 3.2 13
ns
t
PLH
4.7 11.6 15.5 4.7 17
t
PHL
CLK
RCO
3.2 8.1 11 3.2 12.5
ns
t
PLH
1.7 4.1 6 1.7 7
t
PHL
ENT
RCO
1.7 5.6 8 1.7 9
ns
t
PLH
2.7 8.1 11 2.7 12.5
t
PHL
U/D
RCO
3.2 7.6 10.5 3.2 12
ns
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 3: Load circuits and waveforms are shown in Section 1.
SN74F169
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SDFS089 – MARCH 1987 – REVISED OCTOBER 1993
2–8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated
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