Texas Instruments SN74F169D, SN74F169DR, SN74F169N Datasheet
SN74F169
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SDFS089 – MARCH 1987 – REVISED OCTOBER 1993
Copyright 1993, Texas Instruments Incorporated
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• Fully Synchronous Operation for Counting
and Programming
• Internal Look-Ahead Circuitry for Fast
Counting
• Carry Output for N-Bit Cascading
• Fully Independent Clock Circuit
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
This synchronous, presettable, 4-bit up/down binary counter features an internal carry look-ahead circuitry for
cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops
clocked simultaneously so that the outputs change coincident with each other when so instructed by the
count-enable (ENP
, ENT) inputs and internal gating. This mode of operation eliminates the output counting
spikes that are normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input
triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.
This counter is fully programmable; that is, it may be preset to any number between 0 and its maximum count.
The load-input circuitry allows loading with the carry-enable output of cascaded counters. As loading is
synchronous, setting up a low level at the load (LOAD
) input disables the counter and causes the outputs to
agree with the data inputs after the next clock pulse.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous application without
additional gating. Instrumental in accomplishing this function are two count-enable (ENP
, ENT) inputs and a
ripple-carry (RCO
) output. Both ENP and ENT must be low to count. The direction of the count is determined
by the level of the up/down (U/D
) input. When U/D is high, the counter counts up; when low, it counts down. Input
ENT
is fed forward to enable the RCO. RCO thus enabled will produce a low-level pulse while the count is zero
(all inputs low) counting down or maximum (9 or 15) counting up. This low-level overflow ripple-carry pulse can
be used to enable successive cascaded stages. Transitions at ENP
or ENT are allowed regardless of the level
of the clock input. All inputs are diode clamped to minimize transmission-line effects, thereby simplifying system
design.
The SN74F169 features a fully independent clock circuit. Changes at control inputs (ENP
, ENT, LOAD or U/D)
that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The
function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions
meeting the setup and hold times.
The SN74F169 is characterized for operation from 0°C to 70°C.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
U/D
CLK
A
B
C
D
ENP
GND
V
CC
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
D OR N PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74F169
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SDFS089 – MARCH 1987 – REVISED OCTOBER 1993
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
CTRDIV16
LOAD
1, 7D
3
A
4
B
5
C
6
D
M2 [COUNT]
M1 [LOAD]
9
2,3,5,6+/C7
G5
10
15
3,5CT = 15
14
13
12
11
Q
A
Q
B
Q
C
Q
D
G6
7
2
CLK
1
2
4
8
U/D
M4 [DOWN]
M3 [UP]
1
2,4,5,6 –
ENT
ENP
RCO
4,5CT = 0
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN74F169
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SDFS089 – MARCH 1987 – REVISED OCTOBER 1993
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
G2
1
, 2T/C3
1, 3D
M1
9
1
10
7
2
3
15
14
LOAD
U/D
ENT
ENP
CLK
A
RCO
Q
A
G2
1
, 2T/C3
1, 3D
M1
4
13
B
Q
B
G2
1
, 2T/C3
1, 3D
M1
5
12
C
Q
C
G2
1
, 2T/C3
1, 3D
M1
6
11
D
Q
D
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