SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER 1993
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
The SN74F112 contains two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset (PRE
resets the outputs regardless of the levels of the
other inputs. When PRE
(high), data at the J and K inputs meeting the setup
time requirements is transferred to the outputs on
the negative-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse.
Following the hold-time interval, data at the J and
K inputs may be changed without affecting the
levels at the outputs. The SN74F1 12 can perform
as a toggle flip-flop by tying J and K high.
The SN74F1 12 is characterized for operation from
0°C to 70°C.
) or clear (CLR) inputs sets or
and CLR are inactive
PRECLRCLKJKQQ
LHXXXHL
HLXXXLH
LLXXXH
HH↓LLQ
HH↓HLHL
HH↓LHLH
HH↓HHToggle
HHHXXQ
†
The output levels in this configuration are not guaranteed to
meet the minimum levels for VOH. Furthermore, this
configuration is nonstable; that is, it will not persist when
either PRE
FUNCTION TABLE
INPUTS
or CLR returns to its inactive (high) level.
OUTPUTS
†
0
0
D OR N PACKAGE
(TOP VIEW)
1K
1J
1Q
1Q
2Q
†
0
0
1
2
3
4
5
6
7
8
1CLK
1PRE
GND
H
Q
Q
16
15
14
13
12
11
10
9
V
CC
1CLR
2CLR
2CLK
2K
2J
2PRE
2Q
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1993, Texas Instruments Incorporated
2–1
SN74F112
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SDFS048A – D2932, MARCH 1987 – REVISED OCT OBER 1993
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
1PRE
1J
1CLK
1K
1CLR
2PRE
2J
2CLK
2K
2CLR
4
3
1
2
15
10
11
13
12
14
S
1J
C1
1K
R
logic diagram, each flip-flop (positive logic)
5
1Q
6
1Q
9
2Q
7
2Q
QQ
PRE
K
CLK
CLR
J
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSLPeak Temp
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAUN / A for Pkg Type
CU NIPDAUN / A for Pkg Type
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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