TEXAS INSTRUMENTS SN74F112 Technical data
SN74F112
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER 1993
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
The SN74F112 contains two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset (PRE
resets the outputs regardless of the levels of the
other inputs. When PRE
(high), data at the J and K inputs meeting the setup
time requirements is transferred to the outputs on
the negative-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse.
Following the hold-time interval, data at the J and
K inputs may be changed without affecting the
levels at the outputs. The SN74F1 12 can perform
as a toggle flip-flop by tying J and K high.
The SN74F1 12 is characterized for operation from
0°C to 70°C.
) or clear (CLR) inputs sets or
and CLR are inactive
PRE CLR CLK J K Q Q
L H X X X H L
H LXXXLH
LLXXXH
HH↓LLQ
HH↓HLHL
HH↓LHLH
HH↓H H Toggle
H H H X X Q
†
The output levels in this configuration are not guaranteed to
meet the minimum levels for VOH. Furthermore, this
configuration is nonstable; that is, it will not persist when
either PRE
FUNCTION TABLE
INPUTS
or CLR returns to its inactive (high) level.
OUTPUTS
†
0
0
D OR N PACKAGE
(TOP VIEW)
1K
1J
1Q
1Q
2Q
†
0
0
1
2
3
4
5
6
7
8
1CLK
1PRE
GND
H
Q
Q
16
15
14
13
12
11
10
9
V
CC
1CLR
2CLR
2CLK
2K
2J
2PRE
2Q
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1993, Texas Instruments Incorporated
2–1
SN74F112
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SDFS048A – D2932, MARCH 1987 – REVISED OCT OBER 1993
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
1PRE
1J
1CLK
1K
1CLR
2PRE
2J
2CLK
2K
2CLR
4
3
1
2
15
10
11
13
12
14
S
1J
C1
1K
R
logic diagram, each flip-flop (positive logic)
5
1Q
6
1Q
9
2Q
7
2Q
Q Q
PRE
K
CLK
CLR
J
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Input current range –30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state –0.5 V to V
Current into any output in the low state 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
CC
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F112
V
V
twPulse duration
ns
tsuSetup time, data before CLK↓
ns
thHold time, data after CLK↓
ns
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER 1993
recommended operating conditions
MIN NOM MAX UNIT
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
A
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
V
IK
OH
V
OL
I
I
I
IH
I
IL
I
OS
I
CC
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 2: ICC is measured with all outputs open, the Q and Q
Supply voltage 4.5 5 5.5 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
Input clamp current –18 mA
High-level output current –1 mA
Low-level output current 20 mA
Operating free-air temperature 0 70 °C
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VCC = 4.5 V, II = –18 mA –1.2 V
VCC = 4.5 V, IOH = – 1 mA 2.5 3.4
VCC = 4.75 V, IOH = – 1 mA 2.7
VCC = 4.5 V, IOL = 20 mA 0.3 0.5 V
VCC = 5.5 V, VI = 7 V 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 µA
J or K – 0.6
PRE or CLR
CLK – 2.4
‡
VCC = 5.5 V, VI = 0.5 V
VCC = 5.5 V, VO = 0 –60 –150 mA
VCC = 5.5 V, See Note 2 12 19 mA
outputs alternately high and the clock input grounded at the time of measurement.
–3
mA
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
f
clock
t
su
§
Inactive-state state setup time is also referred to as recovery time.
Clock frequency 0 110 0 100 MHz
p
Setup time, inactive state, data before CLK↓
§
TA = 25°C
MIN MAX
CLK high or low 4.5 5
CLR or PRE low 4.5 5
High 4 5
Low 3 3.5
High 0 0
Low 0 0
CLR or PRE high 4 5 ns
MIN MAX UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–3
SN74F112
CLK
Q
Q
ns
PRE or CLR
Q or Q
ns
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SDFS048A – D2932, MARCH 1987 – REVISED OCT OBER 1993
switching characteristics (see Note 3)
VCC = 5 V,
PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
†
NOTE 3: Load circuits and waveforms are shown in Section 1.
PHL
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
FROM
(INPUT)
TO
(OUTPUT)
or
CL = 50 pF,
RL = 500 Ω,
TA = 25°C
MIN TYP MAX MIN MAX
110 130 100 MHz
1.2 4.6 6.5 1.2 7.5
1.2 4.6 6.5 1.2 7.5
1.2 4.1 6.5 1.2 7.5
1.2 4.1 6.5 1.2 7.5
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500Ω,
TA = MIN to MAX
UNIT
†
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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