SN54F02, SN74F02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SDFS036A – MARCH 1987 – REVISED OCT OBER 1993
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These devices contain four independent 2-input
NOR gates. They perform the Boolean functions
Y = A + B
The SN54F02 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F02 is characterized for
operation from 0°C to 70°C.
logic symbol
1A
1B
2A
2B
3A
3B
4A
4B
or Y = A • B in positive logic.
FUNCTION TABLE
(each gate)
INPUTS
A B
H X L
X HL
LLH
†
2
3
5
6
8
9
11
12
≥1
OUTPUT
Y
10
13
SN54F02 ...J PACKAGE
SN74F02 ...D OR N PACKAGE
1B
NC
2Y
NC
2A
1
1Y
4
2Y
3Y
4Y
NC – No internal connection
(TOP VIEW)
1Y
1
1A
2
1B
3
2Y
4
2A
5
2B
6
GND
SN54F02 . . . FK PACKAGE
7
(TOP VIEW)
1A1YNC
3212019
4
5
6
7
8
910111213
2B
GND
14
13
12
11
10
NC
9
8
CC
V
3A
V
4Y
4B
4A
3Y
3B
3A
4Y
18
17
16
15
14
3B
CC
4B
NC
4A
NC
3Y
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
logic diagram (positive logic)
2
1A
3
1B
5
2A
6
2B
8
3A
9
3B
11
4A
12
4B
Pin numbers shown are for the D, J, and N packages.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
13
1
1Y
4
2Y
3Y
4Y
Copyright 1993, Texas Instruments Incorporated
2–1
SN54F02, SN74F02
UNIT
PARAMETER
TEST CONDITIONS
UNIT
V
V
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SDFS036A – MARCH 1987 – REVISED OCT OBER 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Input current range –30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state –0.5 V to V
Current into any output in the low state 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54F02 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74F02 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
SN54F02 SN74F02
MIN NOM MAX MIN NOM MAX
V
V
V
I
I
I
T
CC
IH
IL
IK
OH
OL
A
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input clamp current –18 –18 mA
High-level output current –1 –1 mA
Low-level output current 20 20 mA
Operating free-air temperature –55 125 0 70 °C
†
CC
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54F02 SN74F02
MIN TYP‡MAX MIN TYP‡MAX
V
IK
OH
V
OL
I
I
I
IH
I
IL
§
I
OS
I
CCH
I
‡
§
NOTE 2: I
CCL
All typical values are at VCC = 5 V, TA = 25°C.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
is measured with one input at 4.5 V and all others grounded.
CCL
VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V, IOH = – 1 mA 2.5 3.4 2.5 3.4
VCC = 4.75 V, IOH = – 1 mA 2.7
VCC = 4.5 V, IOL = 20 mA 0.3 0.5 0.3 0.5 V
VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 20 µA
VCC = 5.5 V, VI = 0.5 V – 0.6 – 0.6 mA
VCC = 5.5 V, VO = 0 –60 –150 –60 –150 mA
VCC = 5.5 V, VI = 0 3.7 5.6 3.7 5.6 mA
VCC = 5.5 V, See Note 2 8.7 13 8.7 13 mA
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54F02, SN74F02
(
)
(
)
(INPUT)
(OUTPUT)
A or B
Y
ns
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SDFS036A – MARCH 1987 – REVISED OCTOBER 1993
switching characteristics (see Note 3)
VCC = 5 V,
CL = 50 pF,
PARAMETER
t
PLH
t
†
NOTE 3: Load circuits and waveforms are shown in Section 1.
PHL
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
FROM
INPUT
TO
OUTPUT
RL = 500 Ω,
TA = 25°C
′F02 SN54F02 SN74F02
MIN TYP MAX MIN MAX MIN MAX
1.7 4 5.5 1.7 7.5 1.7 6.5
1 2.8 4.3 1 6.5 1 5.3
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500Ω,
TA = MIN to MAX
†
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–3
SN54F02, SN74F02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SDFS036A – MARCH 1987 – REVISED OCT OBER 1993
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright © 2007, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
5962-9757801Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-9757801QCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
5962-9757801QDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
JM38510/33301BCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
JM38510/33301BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
SN54F02J ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
SN74F02D ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br)
SN74F02DE4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br)
SN74F02DG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br)
SN74F02DR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br)
SN74F02DRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br)
SN74F02DRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br)
SN74F02N ACTIVE PDIP N 14 25 Pb-Free
SN74F02NE4 ACTIVE PDIP N 14 25 Pb-Free
SN74F02NSR ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br)
SN74F02NSRE4 ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br)
SN74F02NSRG4 ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br)
SNJ54F02FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54F02J ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
SNJ54F02W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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to Customer on an annual basis.
9-Oct-2007
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
TAPE AND REEL INFORMATION
11-Mar-2008
*All dimensions are nominal
Device Package
SN74F02DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74F02NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74F02DR SOIC D 14 2500 346.0 346.0 33.0
SN74F02NSR SO NS 14 2000 346.0 346.0 33.0
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A SQ
B SQ
19
20
21
22
23
24
25
12826 27
12
1314151618 17
0.020 (0,51)
0.010 (0,25)
MIN
0.342
(8,69)
0.442
0.640
0.739
0.938
1.141
A
0.358
(9,09)
0.458
(11,63)
0.660
(16,76)
0.761
(19,32)(18,78)
0.962
(24,43)
1.165
(29,59)
NO. OF
TERMINALS
**
11
10
9
8
7
6
5
432
20
28
44
52
68
84
0.020 (0,51)
0.010 (0,25)
(11,23)
(16,26)
(23,83)
(28,99)
MINMAX
0.307
(7,80)
0.406
(10,31)
0.495
(12,58)
0.495
(12,58)
0.850
(21,6)
1.047
(26,6)
0.080 (2,03)
0.064 (1,63)
B
MAX
0.358
(9,09)
0.458
(11,63)
0.560
(14,22)
0.560
(14,22)
0.858
(21,8)
1.063
(27,0)
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
4040140/D 10/96
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