Texas Instruments SN74CBTS3306D, SN74CBTS3306DR, SN74CBTS3306PWLE, SN74CBTS3306PWR Datasheet

SN74CBTS3306

DUAL FET BUS SWITCH

WITH SCHOTTKY DIODE CLAMPING

SCDS029E – JANUARY 1996 – REVISED NOVEMBER 1998

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

5-Ω Switch Connection Between Two Ports

D

TTL-Compatible Input Levels

D

Package Options Include Plastic
Small-Outline (D) and Thin Shrink
Small-Outline (PW) Packages

description

The SN74CBTS3306 features independent line switches with Schottky diodes on the I/Os to clamp undershoot.
Each switch is disabled when the associated output-enable (OE

) input is high.

The SN74CBTS3306 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each bus switch)

INPUT

OE

FUNCTION

L A port = B port

H Disconnect

logic diagram (positive logic)

1A

1B

1OE

2A

2B

2OE

2

1

5

7

3

6

Copyright  1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D OR PW PACKAGE

(TOP VIEW)

1
2
3
4

8
7
6
5

V

CC

2OE
2B
2A

1OE

1A
1B

GND

SN74CBTS3306
DUAL FET BUS SWITCH
WITH SCHOTTKY DIODE CLAMPING

SCDS029E – JANUARY 1996 – REVISED NOVEMBER 1998

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(V

I/O

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 2): D package 197°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 243°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 3)

MIN MAX UNIT

V

CC

Supply voltage 4 5.5 V

V

IH

High-level control input voltage 2 V

V

IL

Low-level control input voltage 0.8 V

T

A

Operating free-air temperature –40 85 °C

NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

A or B inputs

–0.7

V

IK

Control inputs

V

CC

= 4.5 V,

I

I

= –18

mA

–1.2

V

I

IL

VCC = 5.5 V, VI = GND –1

I

I

I

IH

VCC = 5.5 V, VI = 5.5 V

50

µ

A

I

CC

VCC = 5.5 V, IO = 0, VI = VCC or GND 3 µA

∆I

CC

§

Control inputs VCC = 5.5 V, One input at 3.4 V , Other inputs at VCC or GND 2.5 mA

C

i

Control inputs VI = 3 V or 0 5 pF

C

io(OFF)

VO = 3 V or 0, OE = V

CC

6 pF

VCC = 4 V,
TYP at VCC = 4 V

VI = 2.4 V, II = 15 mA 14 20

r

n

¶

II = 64 mA 5 7

Ω

on

VCC = 4.5 V

V

I

=

0

II = 30 mA 5 7

VI = 2.4 V, II = 15 mA 10 15

‡

All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.

§

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

¶

Measured by the voltage drop between the A and B pin at the indicated current through the switch. On-state resistance is determined by the lower
of the voltages of the two (A or B) pins.

SN74CBTS3306

DUAL FET BUS SWITCH

WITH SCHOTTKY DIODE CLAMPING

SCDS029E – JANUARY 1996 – REVISED NOVEMBER 1998

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

VCC = 4 V

VCC = 5 V

± 0.5 V

UNIT

(INPUT)

(OUTPUT)

MIN MAX MIN MAX

t

pd

†

A or B B or A 0.35 0.25 ns

t

en

OE

A or B 5.6 1.8 5 ns

t

dis

OE

A or B 4.6 1 4.3 ns

†

The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

7 V

Open

GND

500 Ω

500 Ω

TEST

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

S1

Open

7 V

0pen

t

PLH

t

PHL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

1.5 V1.5 V

1.5 V 1.5 V

3 V

0 V

1.5 V 1.5 V

V

OH

V

OL

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH – 0.3 V

0 V

Input

3 V

3.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

E. t

PLZ

and t

PHZ

are the same as t

dis

.

F. t

PZL

and t

PZH

are the same as ten.

G. t

PHL

and t

PLH

are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

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Copyright  1998, Texas Instruments Incorporated