Datasheet SN74CBTLV3861DBQR, SN74CBTLV3861DGV, SN74CBTLV3861DGVR, SN74CBTLV3861DW, SN74CBTLV3861DWR Datasheet (Texas Instruments)

SN74CBTLV3861

LOW-VOLTAGE 10-BIT FET BUS SWITCH

SCDS041D – DECEMBER 1997 – REVISED NOVEMBER 1999

D

Functionally Equivalent to QS3861

D

5-Ω Switch Connection Between Two Ports

D

Isolation Under Power-Off Conditions

D

Flow-Through Architecture Optimizes PCB
Layout

D

Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II

D

Package Options Include Shrink
Small-Outline (DBQ), Thin Very
Small-Outline (DGV), Small-Outline (DW),
and Thin Shrink Small-Outline (PW)
Packages

description

The SN74CBTLV3861 provides ten bits of

DBQ, DGV, DW, OR PW PACKAGE

(TOP VIEW)

NC

1

A1

2

A2

3

A3

4

A4

5

A5

6

A6

7

A7

8

A8

9

A9

10

A10

11

GND

NC – No internal connection

12

24
23
22
21
20
19
18
17
16
15
14
13

V

CC

OE
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10

high-speed bus switching. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay.

The device is organized as one 10-bit bus switch. When output enable (OE) is low, the 10-bit bus switch is on
and port A is connected to port B. When OE

is high, the switch is open and the high-impedance state exists

between the two ports.
T o ensure the high-impedance state during power up or power down, OE

should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74CBTLV3861 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUT

OE

L A port = B port

H Disconnect

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FUNCTION

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

1

SN74CBTLV3861
LOW-VOLTAGE 10-BIT FET BUS SWITCH

SCDS041D – DECEMBER 1997 – REVISED NOVEMBER 1999

logic diagram (positive logic)

A1

A10

OE

simplified schematic, each FET switch

A

2

11

23

SW

SW

(OE)

22

13

B1

B10

B

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

Package thermal impedance, θJA (see Note 2): DBQ package 61°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O

IK

DGV package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 88°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

†

2

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VIHHigh-level control input voltage

V

VILLow-level control input voltage

V

V

0

TYP at V

CC

V

§

Ω

V

0

(INPUT)

(OUTPUT)

SN74CBTLV3861

LOW-VOLTAGE 10-BIT FET BUS SWITCH

SCDS041D – DECEMBER 1997 – REVISED NOVEMBER 1999

recommended operating conditions (see Note 3)

MIN MAX UNIT

V

T

NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

V
I

I

I

off

I

CC

∆I
C
C

r

on

†

All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.

‡

This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.

§

Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.

Supply voltage 2.3 3.6 V

CC

p

p

Operating free-air temperature –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

IK

‡

Control inputs VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND 300 µA

CC

Control inputs VI = 3 V or 0 3 pF

i
io(OFF)

VCC = 3 V, II = –18 mA –1.2 V
VCC = 3.6 V, VI = VCC or GND ±1 µA
VCC = 0, VI or VO = 0 to 3.6 V 10 µA
VCC = 3.6 V, IO = 0, VI = VCC or GND 10 µA

VO = 3 V or 0, OE = V

VCC = 2.3 V,

= 2.5

VCC = 3 V

, literature number SCBA004.

CC

=

I

VI = 1.7 V, II = 15 mA 27 40

=

I

VI = 2.4 V, II = 15 mA 10 15

II = 64 mA 5 8
II = 24 mA 5 8

II = 64 mA 5 7
II = 24 mA 5 7

VCC = 2.3 V to 2.7 V 1.7
VCC = 2.7 V to 3.6 V 2
VCC = 2.3 V to 2.7 V 0.7
VCC = 2.7 V to 3.6 V 0.8

5 pF

switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)

PARAMETER

¶

The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).

FROM

¶

t

pd

t

en

t

dis

A or B B or A 0.35 0.25 ns

OE
OE

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TO

A or B 2.1 5.5 2.1 4.9 ns
A or B 1.7 5.5 2.5 5.8 ns

VCC = 2.5 V

± 0.2 V

MIN MAX MIN MAX

VCC = 3.3 V

± 0.3 V

UNIT

3

SN74CBTLV3861
LOW-VOLTAGE 10-BIT FET BUS SWITCH

SCDS041D – DECEMBER 1997 – REVISED NOVEMBER 1999

PARAMETER MEASUREMENT INFORMATION

V

CC

= 2.5 V ± 0.2 V

dis

S1

.

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t

G. t

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

PLZ
PZL
PLH

and t
and t

and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PHL

500 Ω

500 Ω

VCC/2 VCC/2

t

PHL

2 × V

Open

GND

V

0 V

V

V

CC

CC

OH

OL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

VCC/2

Open

2 × V

GND

CC

VCC/2VCC/2

t

PLZ

VOL + 0.15 V

t

PHZ

VOH – 0.15 V

V

0 V

V

V

V

0 V

CC

CC

OL

OH

Figure 1. Load Circuit and Voltage Waveforms

4

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From Output

Under Test

CL = 50 pF

(see Note A)

PARAMETER MEASUREMENT INFORMATION

500 Ω

500 Ω

LOAD CIRCUIT

S1

= 3.3 V ± 0.3 V

V

CC

2 × V

CC

Open

GND

SN74CBTLV3861

LOW-VOLTAGE 10-BIT FET BUS SWITCH

SCDS041D – DECEMBER 1997 – REVISED NOVEMBER 1999

TEST S1

Open

2 × V

GND

CC

V

VCC/2VCC/2

CC

0 V

Output

Control

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t

F. t

G. t

VCC/2 VCC/2

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

PLZ
PZL
PLH

and t
and t

and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PHL

dis

.

Figure 2. Load Circuit and Voltage Waveforms

t

PHL

V

0 V

V

V

CC

OH

OL

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

VCC/2

t

PLZ

VOL + 0.3 V

t

PHZ

VOH – 0.3 V

V

V

V

0 V

CC

OL

OH

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

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Copyright  1999, Texas Instruments Incorporated