Texas Instruments SN74CBTLV3857DBQR, SN74CBTLV3857DGVR, SN74CBTLV3857DW, SN74CBTLV3857DWR, SN74CBTLV3857PWR Datasheet
SN74CBTLV3857
LOW-VOLTAGE 10-BIT FET BUS SWITCH
WITH INTERNAL PULLDOWN RESISTORS
SCDS085B – OCTOBER 1998 – REVISED AUGUST 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Enable Signal Is SSTL_2 Compatible
D
Flow-Through Architecture Optimizes PCB
Layout
D
Designed for Use With 200 Mbit/s Double
Data-Rate (DDR) SDRAM Applications
D
Switch On-State Resistance Is Designed to
Eliminate Series Resistor to DDR SDRAM
D
Internal 10-kΩ Pulldown Resistors to
Ground on B Port
D
Internal 50-kΩ Pullup Resistor on
Output-Enable Input
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
Package Options Include Shrink
Small-Outline (DBQ), Thin Very
Small-Outline (DGV), Small-Outline (DW),
and Thin Shrink Small-Outline (PW)
Packages
description
This 10-bit FET bus switch is designed for 3-V to 3.6-V VCC operation and SSTL_2 output-enable (OE) input
levels.
When OE is low, the 10-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is
open, and the high-impedance state exists between the two ports. There are 10-kΩ pulldown resistors to ground
on the B port.
The FET switch on-state resistance is designed to replace the series terminating resistor in the SSTL_2 data
path.
The SN74CBTLV3857 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUT
OE
FUNCTION
L A port = B port
H Disconnect
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
V
REF
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
GND
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74CBTLV3857
LOW-VOLTAGE 10-BIT FET BUS SWITCH
WITH INTERNAL PULLDOWN RESISTORS
SCDS085B – OCTOBER 1998 – REVISED AUGUST 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
A1
SW
B1
A10
SW
B10
OE
V
REF
R
INT
R
INT
V
CC
2
11
23
1
22
13
simplified schematic, each FET switch
A
(OE)
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range (OE only), VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range (except OE), VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I/O
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DBQ package 103°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 139°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
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