Datasheet SN74CBTLV3383PWR, SN74CBTLV3383DBQR, SN74CBTLV3383DGVR, SN74CBTLV3383DW, SN74CBTLV3383DWR Datasheet (Texas Instruments)

SN74CBTL V3383

LOW-VOLTAGE 10-BIT FET BUS-EXCHANGE SWITCH

SCDS047D – MARCH 1998 – REVISED NOVEMBER 1999

D

Functionally Equivalent to QS3383 and
QS3L383

D

5-Ω Switch Connection Between Two Ports

D

Isolation Under Power-Off Conditions

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

Package Options Include Shrink
Small-Outline (DBQ), Thin Very
Small-Outline (DGV), Small-Outline (DW),
and Thin Shrink Small-Outline (PW)
Packages

DBQ, DGV, DW, OR PW PACKAGE

BE
1B1
1A1
1A2
1B2
2B1
2A1
2A2
2B2
3B1
3A1

GND

(TOP VIEW)

1

24

2

23

3

22

4

21

5

20

6

19

7

18

8

17

9

16

10

15

11

14

12

13

V

CC

5B2
5A2
5A1
5B1
4B2
4A2
4A1
4B1
3B2
3A2
BX

description

The SN74CBTL V3383 provides ten bits of high-speed bus switching or exchanging. The low on-state resistance
of the switch allows connections to be made with minimal propagation delay.

The device operates as a 10-bit bus switch or a 5-bit bus exchanger, which provides swapping of the A and B
pairs of signals. The bus-exchange function is selected when BX is high and BE is low.

The SN74CBTLV3383 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

BE BX 1A1–5A1 1A2–5A2

L L 1B1–5B1 1B2–5B2
L H 1B2–5B2 1B1–5B1

H X Z Z

INPUTS/OUTPUTS

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

1

SN74CBTLV3383
LOW-VOLTAGE 10-BIT FET BUS-EXCHANGE SWITCH

SCDS047D – MARCH 1998 – REVISED NOVEMBER 1999

logic diagram (positive logic)

3

4

21

22

SW

SW

SW

SW

SW

SW

SW

SW

20

23

2

1B11A1

5

1B21A2

5B15A1

5B25A2

1

BE

13

BX

simplified schematic, each FET switch

A

B

(OE)

2

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VIHHigh-level control input voltage

V

VILLow-level control input voltage

V

V

0

TYP at V

CC

V

¶

Ω

V

0

SN74CBTLV3383

LOW-VOLTAGE 10-BIT FET BUS-EXCHANGE SWITCH

SCDS047D – MARCH 1998 – REVISED NOVEMBER 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O

Package thermal impedance, θJA (see Note 2): DBQ package 61°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 88°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 3)

MIN MAX UNIT

V

T

NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2.3 3.6 V

CC

p

p

Operating free-air temperature –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

VCC = 2.3 V to 2.7 V 1.7
VCC = 2.7 V to 3.6 V 2
VCC = 2.3 V to 2.7 V 0.7
VCC = 2.7 V to 3.6 V 0.8

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

V

IK

I

I

I

off

I

CC

§

∆I
C
C

r

on

‡

All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.

§

This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.

¶

Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.

Control inputs VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND 300 µA

CC

Control inputs VI = 3 V or 0 3.5 pF

i
io(OFF)

VCC = 3 V, II = –18 mA –1.2 V
VCC = 3.6 V, VI = VCC or GND ±1 µA
VCC = 0, VI or VO= 0 to 3.6 V 10 µA
VCC = 3.6 V, IO = 0, VI = VCC or GND 10 µA

VO = 3 V or 0, BE = V

VCC = 2.3 V,

= 2.5

VCC = 3 V

=

I

VI = 1.7 V, II = 15 mA 27 40

=

I

VI = 2.4 V, II = 15 mA 10 15

CC

II = 64 mA 5 8
II = 24 mA 5 8

II = 64 mA 5 7
II = 24 mA 5 7

13.5 pF

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3

SN74CBTLV3383

(INPUT)

(OUTPUT)

LOW-VOLTAGE 10-BIT FET BUS-EXCHANGE SWITCH

SCDS047D – MARCH 1998 – REVISED NOVEMBER 1999

switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)

PARAMETER

†

t

pd

t

pd

t

en

t

dis

†

The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance when
driven by an ideal voltage source (zero output impedance).

FROM

A or B B or A 0.15 0.25 ns

BX
BE
BE

TO

A or B 1.5 5.8 1.5 4.7 ns
A or B 1.5 5.3 1.5 4.7 ns
A or B 1 6 1 6 ns

VCC = 2.5 V

± 0.2 V

MIN MAX MIN MAX

PARAMETER MEASUREMENT INFORMATION

= 2.5 V ± 0.2 V

V

CC

VCC = 3.3 V

± 0.3 V

UNIT

dis

S1

.

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t

G. t

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

PLZ
PZL
PLH

and t
and t

and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PHL

500 Ω

500 Ω

VCC/2 VCC/2

t

PHL

2 × V

Open

GND

V

0 V

V

V

CC

CC

OH

OL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

VCC/2

Open

2 × V

GND

CC

VCC/2VCC/2

t

PLZ

VOL + 0.15 V

t

PHZ

VOH – 0.15 V

V

0 V

V

V

V

0 V

CC

CC

OL

OH

4

Figure 1. Load Circuit and Voltage Waveforms

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From Output

Under Test

CL = 50 pF

(see Note A)

PARAMETER MEASUREMENT INFORMATION

500 Ω

500 Ω

LOAD CIRCUIT

S1

SN74CBTLV3383

LOW-VOLTAGE 10-BIT FET BUS-EXCHANGE SWITCH

SCDS047D – MARCH 1998 – REVISED NOVEMBER 1999

= 3.3 V ± 0.3 V

V

CC

2 × V

CC

Open

GND

Output

Control

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

Open

2 × V

GND

CC

VCC/2VCC/2

V

0 V

CC

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.

E. t
F. t

G. t

VCC/2 VCC/2

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

PLZ
PZL
PLH

and t
and t

and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PHL

dis

.

Figure 2. Load Circuit and Voltage Waveforms

t

PHL

V

0 V

V

V

CC

OH

OL

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

VCC/2

t

PLZ

VOL + 0.3 V

t

PHZ

VOH – 0.3 V

V

V

V

0 V

CC

OL

OH

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5

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