SN74CBTLV3257
LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999
D
Functionally Equivalent to QS3257
D
5-Ω Switch Connection Between Two Ports
D
Isolation Under Power-Off Conditions
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
Package Options Include Thin Very
Small-Outline (DGV), Small-Outline (D),
D, DBQ, DGV, OR PW PACKAGE
1B1
1B2
1A
2B1
2B2
2A
GND
(TOP VIEW)
1
S
2
3
4
5
6
7
8
16
15
14
13
12
11
10
V
CC
OE
4B1
4B2
4A
3B1
3B2
9
3A
Shrink Small-Outline (DBQ), and Thin
Shrink Small-Outline (PW) Packages
description
The SN74CBTL V3257 is a 4-bit 1-of-2 high-speed FET multiplexer/demultiplexer . The low on-state resistance
of the switch allows connections to be made with minimal propagation delay.
The select (S) input controls the data flow. The FET multiplexers/demultiplexers are disabled when the
output-enable (OE) input is high.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74CBTLV3257 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OE S
L L A port = B1 port
L H A port = B2 port
H X Disconnect
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN74CBTLV3257
LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999
logic diagram (positive logic)
4
7
9
12
SW
SW
SW
SW
SW
SW
SW
SW
11
10
14
13
2
1B11A
3
1B2
5
2B12A
6
2B2
3B13A
3B2
4B14A
4B2
1
S
15
OE
simplified schematic, each FET switch
A
B
(OE)
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265