Datasheet SN74CBTLV3257DGVR, SN74CBTLV3257DR, SN74CBTLV3257PWR, SN74CBTLV3257D, SN74CBTLV3257DBQR Datasheet (Texas Instruments)

FUNCTION

SN74CBTLV3257

LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER

SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999

D

Functionally Equivalent to QS3257

D

5-Ω Switch Connection Between Two Ports

D

Isolation Under Power-Off Conditions

D

ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)

D

Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II

D

Package Options Include Thin Very
Small-Outline (DGV), Small-Outline (D),

D, DBQ, DGV, OR PW PACKAGE

1B1
1B2

1A
2B1
2B2

2A

GND

(TOP VIEW)

1

S

2
3
4
5
6
7
8

16
15
14
13
12
11
10

V

CC

OE
4B1
4B2
4A
3B1
3B2

9

3A

Shrink Small-Outline (DBQ), and Thin
Shrink Small-Outline (PW) Packages

description

The SN74CBTL V3257 is a 4-bit 1-of-2 high-speed FET multiplexer/demultiplexer . The low on-state resistance
of the switch allows connections to be made with minimal propagation delay.

The select (S) input controls the data flow. The FET multiplexers/demultiplexers are disabled when the
output-enable (OE) input is high.

T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBTLV3257 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

OE S

L L A port = B1 port
L H A port = B2 port

H X Disconnect

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

1

SN74CBTLV3257
LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER

SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999

logic diagram (positive logic)

4

7

9

12

SW

SW

SW

SW

SW

SW

SW

SW

11

10

14

13

2

1B11A

3

1B2

5

2B12A

6

2B2

3B13A

3B2

4B14A

4B2

1

S

15

OE

simplified schematic, each FET switch

A

B

(OE)

2

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VIHHigh-level control input voltage

V

VILLow-level control input voltage

V

C

V

3 V

OE

V

pF

V

0

TYP at V

CC

V

r

¶

Ω

V

0

SN74CBTLV3257

LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER

SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O

Package thermal impedance, θJA (see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DBQ package 90°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 3)

MIN MAX UNIT

V

T

NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2.3 3.6 V

CC

p

p

Operating free-air temperature –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

VCC = 2.3 V to 2.7 V 1.7
VCC = 2.7 V to 3.6 V 2
VCC = 2.3 V to 2.7 V 0.7
VCC = 2.7 V to 3.6 V 0.8

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

V

IK

I

I

I

off

I

CC

§

∆I

CC

C

i

io(OFF)

on

‡

All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.

§

This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.

¶

Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined
by the lower of the voltages of the two (A or B) terminals.

Control inputs VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND 300 µA
Control inputs VI = 3 V or 0 3 pF
A port
B port

VCC = 3 V, II = –18 mA –1.2 V
VCC = 3.6 V, VI = VCC or GND ±1 µA
VCC = 0, VI or VO= 0 to 4.5 V 10 µA
VCC = 3.6 V, IO = 0, VI = VCC or GND 10 µA

or 0,

=

O

VCC = 2.3 V,

VCC = 3 V

= 2.5

=

CC

=

I

VI = 1.7 V, II = 15 mA 27 40

=

I

VI = 2.4 V, II = 15 mA 10 15

II = 64 mA 5 8
II = 24 mA 5 8

II = 64 mA 5 7
II = 24 mA 5 7

5.5

10.5

p

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3

SN74CBTLV3257

(INPUT)

(OUTPUT)

LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER

SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999

switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)

PARAMETER

t

pd

t

en

t

dis

t

en

t

dis

†

The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).

FROM

A or B

S
S

S
OE
OE

†

TO

B or A 0.35 0.25
A or B 1.8 6.1 1.8 5.3
A or B 1.7 6.1 1.7 5.3 ns
A or B 1 4.8 1 4.5 ns
A or B 1.9 5.6 2 5 ns
A or B 1 5.5 1.6 5.5 ns

VCC = 2.5 V

± 0.2 V

MIN MAX MIN MAX

PARAMETER MEASUREMENT INFORMATION

V

= 2.5 V ± 0.2 V

CC

VCC = 3.3 V

± 0.3 V

UNIT

ns

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t

G. t

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

and t

PLZ
PZL
PLH

and t

and t

PHZ
PZH

PHL

500 Ω

500 Ω

VCC/2 VCC/2

are the same as t
are the same as ten.
are the same as tpd.

S1

dis

.

2 × V

Open

GND

t

PHL

CC

V

0 V

V

V

CC

OH

OL

Output

Control

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

VCC/2

Open

2 × V

GND

CC

VCC/2VCC/2

t

PLZ

VOL + 0.15 V

t

PHZ

VOH – 0.15 V

V

0 V

V

V

V

0 V

CC

CC

OL

OH

4

Figure 1. Load Circuit and Voltage Waveforms

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From Output

Under Test

CL = 50 pF

(see Note A)

PARAMETER MEASUREMENT INFORMATION

500 Ω

500 Ω

LOAD CIRCUIT

SN74CBTLV3257

LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER

SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999

= 3.3 V ± 0.3 V

V

CC

2 × V

S1

CC

Open

GND

Output

Control

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

Open

2 × V

GND

CC

V

VCC/2VCC/2

CC

0 V

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.

E. t
F. t

G. t

VCC/2 VCC/2

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

PLZ
PZL
PLH

and t
and t

and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PHL

dis

.

Figure 2. Load Circuit and Voltage Waveforms

t

PHL

V

0 V

V

V

CC

OH

OL

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

VCC/2

t

PLZ

VOL + 0.3 V

t

PHZ

VOH – 0.3 V

V

V

V

0 V

CC

OL

OH

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5

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Copyright  1999, Texas Instruments Incorporated