Texas Instruments SN74CBTLV3253D, SN74CBTLV3253DBQR, SN74CBTLV3253DGVR, SN74CBTLV3253DR, SN74CBTLV3253PWR Datasheet

FUNCTION
SN74CBTLV3253
LOW-VOLTAGE DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
SCDS039D – DECEMBER 1997 – REVISED AUGUST 1999
D
Functionally Equivalent to QS3253
D
D
Isolation Under Power-Off Conditions
D
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
D
Package Options Include Small-Outline (D), Shrink Small-Outline (DBQ), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages
D, DBQ, DGV, OR PW PACKAGE
1OE
S1 1B4 1B3 1B2 1B1
1A
GND
(TOP VIEW)
16
1
15
2
14
3
13
4
12
5
11
6
10
7 8
V
CC
2OE S0 2B4 2B3 2B2 2B1
9
2A
description
The SN74CBTL V3253 is a dual 1-of-4 high-speed FET multiplexer/demultiplexer . The low on-state resistance of the switch allows connections to be made with minimal propagation delay.
The select (S0, S1) inputs control the data flow. The FET multiplexers/demultiplexers are disabled when the associated output-enable (OE) input is high.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74CBTLV3253 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each multiplexer/demultiplexer)
INPUTS
OE
S1 S0
L L L A port = B1 port L L H A port = B2 port L H L A port = B3 port L H H A port = B4 port
H X X Disconnect
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN74CBTLV3253 LOW-VOLTAGE DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
SCDS039D – DECEMBER 1997 – REVISED AUGUST 1999
logic diagram (positive logic)
1A
2A
S0
S1
7
9
14
2
SW
SW
SW
SW
SW
SW
SW
SW
10
11
12
13
6
1B1
5
1B2
4
1B3
3
1B4
2B1
2B2
2B3
2B4
1
1OE
15
2OE
simplified schematic, each FET switch
A
B
(OE)
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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