Texas Instruments SN74CBTLV3245DBLE, SN74CBTLV3245DBR, SN74CBTLV3245DGVR, SN74CBTLV3245PWLE, SN74CBTLV3245PWR Datasheet
SN74CBTLV3245
LOW-VOLTAGE OCTAL FET BUS SWITCH
SCDS034F – JULY 1997 – REVISED MAY 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Standard ’245-Type Pinout
D
5-Ω Switch Connection Between Two Ports
D
Isolation Under Power-Off Conditions
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Shrink
Small-Outline (DB), Thin Very Small-Outline
(DGV), Small-Outline (DW), and Thin Shrink
Small-Outline (PW) Packages
description
The SN74CBTLV3245 provides eight bits of
high-speed bus switching in a standard ’245
device pinout. The low on-state resistance of the
switch allows connections to be made with
minimal propagation delay.
The device is organized as one 8-bit switch. When output enable (OE
) is low, the 8-bit bus switch is on and
port A is connected to port B. When OE
is high, the switch is open and a high-impedance state exists between
the two ports.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74CBTLV3245 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUT
OE
FUNCTION
L A port = B port
H Disconnect
logic diagram (positive logic)
A1
SW
B1
A8
OE
SW
B8
2
9
19
18
11
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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NC
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
DB, DGV, DW, OR PW PACKAGE
(TOP VIEW)
NC – No internal connection
SN74CBTLV3245
LOW-VOLTAGE OCTAL FET BUS SWITCH
SCDS034F – JULY 1997 – REVISED MAY 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
simplified schematic, each FET switch
A
(OE)
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I/O
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 146°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
Supply voltage 2.3 3.6 V
p
VCC = 2.3 V to 2.7 V 1.7
VIHHigh-level control input voltage
VCC = 2.7 V to 3.6 V 2
V
p
VCC = 2.3 V to 2.7 V 0.7
VILLow-level control input voltage
VCC = 2.7 V to 3.6 V 0.8
V
T
A
Operating free-air temperature –40 85 °C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
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