Datasheet SN74CBTLV3245ADBQR, SN74CBTLV3245ADGVR, SN74CBTLV3245ADW, SN74CBTLV3245ADWR, SN74CBTLV3245APWR Datasheet (Texas Instruments)

FUNCTION

SN74CBTLV3245A

LOW-VOLTAGE OCTAL FET BUS SWITCH

SCDS034H – JULY 1997 – REVISED NOVEMBER 1999

D

Standard ’245-Type Pinout

D

5-Ω Switch Connection Between Two Ports

D

Isolation Under Power-Off Conditions

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

Package Options Include Shrink
Small-Outline (DBQ), Thin Very
Small-Outline (DGV), Small-Outline (DW),
and Thin Shrink Small-Outline (PW)

DBQ, DGV, DW, OR PW PACKAGE

NC

A1
A2
A3
A4
A5
A6
A7
A8

GND

(TOP VIEW)

20

1

19

2

18

3

17

4

16

5

15

6

14

7

13

8

12

9

11

10

V
OE
B1
B2
B3
B4
B5
B6
B7
B8

CC

Packages

NC – No internal connection

description

The SN74CBTL V3245A provides eight bits of high-speed bus switching in a standard ’245 device pinout. The
low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device is organized as one 8-bit switch. When output enable (OE) is low, the 8-bit bus switch is on and A port
is connected to B port. When OE
two ports.

T o ensure the high-impedance state during power up or power down, OE
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

is high, the switch is open and the high-impedance state exists between the

should be tied to VCC through a pullup

The SN74CBTLV3245A is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUT

OE

L A port = B port

H Disconnect

logic diagram (positive logic)

2

A1

A8

OE

9

19

SW

SW

18

11

B1

B8

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

1

SN74CBTLV3245A

VIHHigh-level control input voltage

V

VILLow-level control input voltage

V

LOW-VOLTAGE OCTAL FET BUS SWITCH

SCDS034H – JULY 1997 – REVISED NOVEMBER 1999

simplified schematic, each FET switch

A

(OE)

B

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I
Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O

(see Note 2): DBQ package 68°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

IK

DGV package 92°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

†

recommended operating conditions (see Note 3)

MIN MAX UNIT

V

T

NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2.3 3.6 V

CC

p

p

Operating free-air temperature –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

VCC = 2.3 V to 2.7 V 1.7
VCC = 2.7 V to 3.6 V 2
VCC = 2.3 V to 2.7 V 0.7
VCC = 2.7 V to 3.6 V 0.8

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

V

V

3 V

I

18 mA

V

V

0

TYP at V

CC

V

§

Ω

V

0

(INPUT)

(OUTPUT)

SN74CBTLV3245A

LOW-VOLTAGE OCTAL FET BUS SWITCH

SCDS034H – JULY 1997 – REVISED NOVEMBER 1999

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

Control inputs

IK

Data inputs

I

I

I

off

I

CC

‡

∆I
C
C

r

on

†

All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.

‡

This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.

§

Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.

Control inputs VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND 300 µA

CC

Control inputs VI = 3 V or 0 4 pF

i
io(OFF)

CC

VCC = 3.6 V, VI = VCC or GND ±60 µA
VCC = 0, VI or VO = 0 to 3.6 V 40 µA
VCC = 3.6 V, IO = 0, VI = VCC or GND 20 µA

VO = 3 V or 0, OE = V

VCC = 2.3 V,

VCC = 3 V

=

,

= 2.5

= –

I

CC

=

I

VI = 1.7 V, IO = 15 mA 27 40

=

I

VI = 2.4 V, IO = 15 mA 10 15

IO = 64 mA 5 8
IO = 24 mA 5 8

IO = 64 mA 5 7
IO = 24 mA 5 7

–1.2
–0.8

9 pF

switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)

PARAMETER

¶

t

pd

t

en

t

dis

¶

The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance when
driven by an ideal voltage source (zero output impedance).

FROM

A or B B or A 0.15 0.25 ns

OE
OE

TO

A or B 1 6 1 4.7 ns
A or B 1 6.1 1 6.4 ns

VCC = 2.5 V

± 0.2 V

MIN MAX MIN MAX

VCC = 3.3 V

± 0.3 V

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN74CBTLV3245A
LOW-VOLTAGE OCTAL FET BUS SWITCH

SCDS034H – JULY 1997 – REVISED NOVEMBER 1999

PARAMETER MEASUREMENT INFORMATION

V

CC

= 2.5 V ± 0.2 V

dis

S1

.

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t

F. t

G. t

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

PLZ
PZL
PLH

and t
and t

and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PHL

500 Ω

500 Ω

VCC/2 VCC/2

t

PHL

2 × V

Open

GND

V

0 V

V

V

CC

CC

OH

OL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

VCC/2

Open

2 × V

GND

CC

VCC/2VCC/2

t

PLZ

VOL + 0.15 V

t

PHZ

VOH – 0.15 V

V

0 V

V

V

V

0 V

CC

CC

OL

OH

Figure 1. Load Circuit and Voltage Waveforms

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

From Output

Under Test

CL = 50 pF

(see Note A)

PARAMETER MEASUREMENT INFORMATION

500 Ω

500 Ω

LOAD CIRCUIT

S1

= 3.3 V ± 0.3 V

V

CC

2 × V

CC

Open

GND

SN74CBTLV3245A

LOW-VOLTAGE OCTAL FET BUS SWITCH

SCDS034H – JULY 1997 – REVISED NOVEMBER 1999

TEST S1

Open

2 × V

GND

CC

V

VCC/2VCC/2

CC

0 V

Output

Control

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.

E. t
F. t

G. t

VCC/2 VCC/2

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

PLZ
PZL
PLH

and t
and t

and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PHL

dis

.

Figure 2. Load Circuit and Voltage Waveforms

t

PHL

V

0 V

V

V

CC

OH

OL

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

VCC/2

t

PLZ

VOL + 0.3 V

t

PHZ

VOH – 0.3 V

V

V

V

0 V

CC

OL

OH

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1999, Texas Instruments Incorporated