Texas Instruments SN74CBTLV3125D, SN74CBTLV3125DBQR, SN74CBTLV3125DGVR, SN74CBTLV3125DR, SN74CBTLV3125PWR Datasheet
SN74CBTLV3125
LOW-VOLTAGE QUADRUPLE FET BUS SWITCH
SCDS037D – DECEMBER 1997 – REVISED JUL Y 1999
D
Standard ’125-Type Pinout
D
5-Ω Switch Connection Between Two Ports
D
Isolation Under Power-Off Conditions
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DBQ), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages
description
The SN74CBTL V3125 quadruple FET bus switch
features independent line switches. Each switch
is disabled when the associated output-enable
(OE
) input is high.
T o ensure the high-impedance state during power
up or power down, OE should be tied to V
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
The SN74CBTLV3125 is characterized for
operation from –40°C to 85°C.
CC
D, DGV, OR PW PACKAGE
(TOP VIEW)
16
15
14
13
12
11
10
14
13
12
11
10
V
CC
4OE
4A
4B
3OE
9
3A
8
3B
V
CC
4OE
4A
4B
3OE
3A
3B
9
NC
1OE
1
1A
2
1B
3
4
2OE
5
2A
6
2B
GND
GND
NC – No internal connection
7
DBQ PACKAGE
(TOP VIEW)
1
NC
2
1OE
3
1A
4
1B
5
2OE
6
2A
7
2B
8
FUNCTION TABLE
(each bus switch)
INPUT
OE
L A port = B port
H Disconnect
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FUNCTION
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN74CBTLV3125
LOW-VOLTAGE QUADRUPLE FET BUS SWITCH
SCDS037D – DECEMBER 1997 – REVISED JUL Y 1999
logic diagram (positive logic)
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
Pin numbers shown are for the D, DGV, and PW packages.
simplified schematic, each FET switch
SW
SW
SW
SW
3
1B
6
2B
8
3B
11
4B
A
(OE)
B
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VIHHigh-level control input voltage
V
VILLow-level control input voltage
V
V
2.3 V
V
0
TYP at V
CC
V
¶
Ω
V
0
SN74CBTLV3125
LOW-VOLTAGE QUADRUPLE FET BUS SWITCH
SCDS037D – DECEMBER 1997 – REVISED JUL Y 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O
Package thermal impedance, θJA (see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DBQ package 139°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 182°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
T
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2.3 3.6 V
CC
p
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 2.3 V to 2.7 V 1.7
VCC = 2.7 V to 3.6 V 2
VCC = 2.3 V to 2.7 V 0.7
VCC = 2.7 V to 3.6 V 0.8
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
V
IK
I
I
I
off
I
CC
§
∆I
C
C
r
on
‡
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
§
This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
¶
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
Control inputs VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND 300 µA
CC
Control inputs VI = 3 V or 0 2.5 pF
i
io(OFF)
VCC = 3 V, II = –18 mA –1.2 V
VCC = 3.6 V, VI = VCC or GND ±1 µA
VCC = 0, VI or VO= 0 to 4.5 V 10 µA
VCC = 3.6 V, IO = 0, VI = VCC or GND 10 µA
VO = 3 V or 0, OE = V
=
CC
VCC = 3 V
,
= 2.5
=
=
I
VI = 1.7 V, II = 15 mA 27 40
=
I
VI = 2.4 V, II = 15 mA 10 15
CC
II = 64 mA 5 8
II = 24 mA 5 8
II = 64 mA 5 7
II = 24 mA 5 7
7 pF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74CBTLV3125
(INPUT)
(OUTPUT)
LOW-VOLTAGE QUADRUPLE FET BUS SWITCH
SCDS037D – DECEMBER 1997 – REVISED JUL Y 1999
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
PARAMETER
†
t
pd
t
en
t
dis
†
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
FROM
A or B B or A 0.35 0.25 ns
OE
OE
TO
A or B 2 4.6 2 4.4 ns
A or B 1.1 3.9 1 4.2 ns
VCC = 2.5 V
± 0.2 V
MIN MAX MIN MAX
PARAMETER MEASUREMENT INFORMATION
V
= 2.5 V ± 0.2 V
CC
2 × V
From Output
Under Test
CL = 30 pF
(see Note A)
500 Ω
500 Ω
S1
CC
Open
GND
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
VCC = 3.3 V
± 0.3 V
Open
2 × V
CC
GND
UNIT
LOAD CIRCUIT
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
VCC/2 VCC/2
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 1. Load Circuit and Voltage Waveforms
t
PHL
V
0 V
V
V
CC
OH
OL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
V
0 V
V
V
V
0 V
CC
CC
OL
OH
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTLV3125
LOW-VOLTAGE QUADRUPLE FET BUS SWITCH
SCDS037D – DECEMBER 1997 – REVISED JUL Y 1999
PARAMETER MEASUREMENT INFORMATION
= 3.3 V ± 0.3 V
V
CC
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
and t
PLZ
PZL
PLH
and t
and t
PHZ
PZH
PHL
500 Ω
500 Ω
VCC/2 VCC/2
are the same as t
are the same as ten.
are the same as tpd.
S1
dis
.
6 V
GND
t
PHL
Open
V
0 V
V
V
CC
OH
OL
Output
Control
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
Open
2 × V
GND
CC
VCC/2VCC/2
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
V
0 V
V
V
V
0 V
CC
CC
OL
OH
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
Loading...