Datasheet SN74CBTLV16800GR, SN74CBTLV16800VR, SN74CBTLV16800DL, SN74CBTLV16800DLR Datasheet (Texas Instruments)

SN74CBTLV16800

LOW-VOLTAGE 20-BIT FET BUS SWITCH

WITH PRECHARGED OUTPUTS

SCDS045F – DECEMBER 1997 – REVISED MA Y 1999

D

5-Ω Switch Connection Between Two Ports

D

Isolation Under Power-Off Conditions

D

B-Port Outputs Are Precharged by Bias
Voltage to Minimize Signal Distortion
During Live Insertion

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II

D

Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and 300-mil Shrink
Small-Outline (DL) Packages

NOTE: For tape and reel order entry:

The DGGR package is abbreviated to GR, and
the DGVR package is abbreviated to VR.

description

The SN74CBTLV16800 provides 20 bits of
high-speed bus switching. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay . The device
also precharges the B port to a user-selectable
bias voltage (BIASV) to minimize live-insertion
noise.

DGG, DGV, OR DL PACKAGE

BIASV

1A1
1A2
1A3
1A4
1A5
1A6

GND

1A7
1A8
1A9

1A10

2A1
2A2

V

CC

2A3

GND

2A4
2A5
2A6
2A7
2A8
2A9

2A10

(TOP VIEW)

1

48

2

47

3

46

4

45

5

44

6

43

7

42

8

41

9

40

10

39

11

38

12

37

13

36

14

35

15

34

16

33

17

32

18

31

19

30

20

29

21

28

22

27

23

26

24

25

1OE
2OE
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
1B9
1B10
2B1
2B2
2B3
GND
2B4
2B5
2B6
2B7
2B8
2B9
2B10

The device is organized as dual 10-bit bus switches with separate output-enable (OE
as two 10-bit bus switches or one 20-bit bus switch. When OE
and port A is connected to port B. When OE

is high, the switch is open, the high-impedance state exists between

is low, the associated 10-bit bus switch is on,

) inputs. It can be used

the two ports, and port B is precharged to BIASV through the equivalent of a 10-kΩ resistor.
T o ensure the high-impedance state during power up or power down, OE

should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74CBTLV16800 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each 10-bit bus switch)

INPUT

OE

L A port = B port
H

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FUNCTION

A port = Z

B port = BIASV

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

1

SN74CBTLV16800
LOW-VOLTAGE 20-BIT FET BUS SWITCH
WITH PRECHARGED OUTPUTS

SCDS045F – DECEMBER 1997 – REVISED MA Y 1999

logic diagram (positive logic)

1A1

2

SW

46

1

BIASV

1B1

12

1A10

48

1OE

13

2A1

24

2A10

47

2OE

simplified schematic, each FET switch

SW

SW

SW

36

1B10

35

2B1

25

2B10

A

(OE)

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

B

VIHHigh-level control input voltage

V

VILLow-level control input voltage

V

V

2.3 V

V

0

TYP at V

CC

V

¶

Ω

V

0

SN74CBTLV16800

LOW-VOLTAGE 20-BIT FET BUS SWITCH

WITH PRECHARGED OUTPUTS

SCDS045F – DECEMBER 1997 – REVISED MA Y 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

†

Bias voltage range, BIASV –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I
Package thermal impedance, θ

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(see Note 2): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DGV package 93°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 3)

MIN MAX UNIT

V
BIASV Bias voltage 1.3 V

T

NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2.3 3.6 V

CC

p

p

Operating free-air temperature –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

VCC = 2.3 V to 2.7 V 1.7
VCC = 2.7 V to 3.6 V 2
VCC = 2.3 V to 2.7 V 0.7
VCC = 2.7 V to 3.6 V 0.8

CC

V

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

V

IK

I

I

I

off

I

O

I

CC

∆I

CC

C

i

C

io(OFF)

r

on

‡

All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.

§

This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.

¶

Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.

A port VCC = 0, VI or VO= 0 to 3.6 V 10 µA

§

Control inputs VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND 300 µA
Control inputs VI = 3 V or 0 4.5 pF

VCC = 3 V, II = –18 mA –1.2 V
VCC = 3.6 V, VI = VCC or GND ±1 µA

VCC = 3 V, BIASV = 2.4 V, VO= 0, OE = V
VCC = 3.6 V, IO = 0, VI = VCC or GND 10 µA

VO = 3 V or 0, Switch off, BIASV = Open 6.5 pF

=

CC

VCC = 3 V

,
= 2.5

=

=

I

VI = 1.7 V, II = 15 mA 25 35

=

I

VI = 2.4 V, II = 15 mA 8 15

II = 64 mA 5 9
II = 24 mA 5 9

II = 64 mA 5 7
II = 24 mA 5 7

CC

0.25 mA

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3

SN74CBTLV16800

CONDITIONS

(INPUT)

(OUTPUT)

OE

A or B

ns

OE

A or B

ns

LOW-VOLTAGE 20-BIT FET BUS SWITCH
WITH PRECHARGED OUTPUTS

SCDS045F – DECEMBER 1997 – REVISED MA Y 1999

switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)

PARAMETER

†

t

pd

t

PZH

t

PZL

t

PHZ

t

PLZ

†

The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).

TEST

BIASV = GND

BIASV = 3 V

BIASV = GND

BIASV = 3 V

FROM

A or B B or A 0.35 0.25 ns

TO

VCC = 2.5 V

± 0.2 V

MIN MAX MIN MAX

2.9 7.7 2.2 5.5

2.8 6.4 2.1 5.3

1.4 6.8 2.6 7.6

1.3 4.2 1.5 5.1

PARAMETER MEASUREMENT INFORMATION

V

= 2.5 V ± 0.2 V

CC

2 × V

From Output

Under Test

CL = 30 pF

(see Note A)

500 Ω

500 Ω

S1

CC

Open

GND

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

VCC = 3.3 V

± 0.3 V

Open

2 × V

CC

GND

UNIT

LOAD CIRCUIT

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t

VCC/2 VCC/2

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

PLH

and t

are the same as tpd.

PHL

Figure 1. Load Circuit and Voltage Waveforms

t

PHL

V

0 V

V

V

CC

OH

OL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

VCC/2

VCC/2VCC/2

t

PLZ

VOL + 0.15 V

t

PHZ

VOH – 0.15 V

V

0 V

V

V

V

0 V

CC

CC

OL

OH

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74CBTLV16800

LOW-VOLTAGE 20-BIT FET BUS SWITCH

WITH PRECHARGED OUTPUTS

SCDS045F – DECEMBER 1997 – REVISED MA Y 1999

PARAMETER MEASUREMENT INFORMATION

V

= 3.3 V ± 0.3 V

CC

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

E. t
F. t

G. t

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

and t

PLZ
PZL
PLH

and t

and t

PHZ
PZH

PHL

500 Ω

500 Ω

1.5 V 1.5 V

are the same as t
are the same as ten.

are the same as tpd.

dis

.

S1

t

PHL

6 V

Open

GND

3 V

0 V

V

OH

V

OL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

1.5 V 1.5 V

t

PZL

1.5 V

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Open

6 V

GND

1.5 V

t

PLZ

VOL + 0.3 V

t

PHZ

VOH – 0.3 V

3 V

0 V

3 V

V

V

0 V

OL

OH

Figure 2. Load Circuit and Voltage Waveforms

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5

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Copyright  1999, Texas Instruments Incorporated