LOW-VOLTAGE 12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
SCDS055G – MARCH 1998 – REVISED APRIL 1999
D
4-Ω Switch Connection Between Two Ports
D
Isolation Under Power-Off Conditions
D
Make-Before-Break Feature
D
Internal 500-Ω Pulldown Resistors to
Ground
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and 300-mil Shrink
Small-Outline (DL) Packages
description
The SN74CBTLV16292 is a 12-bit 1-of-2
high-speed FET multiplexer/demultiplexer. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
delay .
When the select (S) input is low, port A is
connected to port B1 and R
port B2. When S is high, port A is connected to
port B2 and R
is connected to port B1.
INT
The SN74CBTLV16292 is characterized for
operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN74CBTLV16292
LOW-VOLTAGE 12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
SCDS055G – MARCH 1998 – REVISED APRIL 1999
logic diagram (positive logic)
1A
12A
2
27
SW
SW
SW
54
1B1
R
INT
R
INT
53
1B2
30
12B1
R
INT
R
INT
1
S
simplified schematic, each FET switch
A
SW
(OE)
29
12B2
B
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VIHHigh-level control input voltage
V
VILLow-level control input voltage
V
V
V
0
TYP at V
CC
V
r
¶
Ω
V
0
SN74CBTLV16292
LOW-VOLTAGE 12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
SCDS055G – MARCH 1998 – REVISED APRIL 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage2.33.6V
CC
p
p
Operating free-air temperature–4085°C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 2.3 V to 2.7 V1.7
VCC = 2.7 V to 3.6 V2
VCC = 2.3 V to 2.7 V0.7
VCC = 2.7 V to 3.6 V0.8
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETERTEST CONDITIONSMIN TYP‡MAXUNIT
V
IK
I
I
I
off
I
CC
§
∆I
CC
C
i
C
io
on
‡
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
§
This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
¶
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
Control inputVCC = 3.6 V,One input at 3 V,Other inputs at VCC or GND300µA
Control inputVI = 3.3 V or 03.5pF
A or B portVO = 3.3 V or 022.5pF
VCC = 3 V,II = –18 mA–1.2V
VCC = 3.6 V,VI = VCC or GND±1µA
VCC = 0,VI or VO = 0 to 3.6 V10µA
VCC = 3.6 V,IO = 0,VI = VCC or GND10µA
= 2.3 V,
CC
VCC = 3 V
=
= 2.5
=
I
VI = 1.7 V,II = 15 mA1140
=
I
VI = 2.4 V,II = 15 mA715
II = 64 mA58
II = 24 mA58
II = 64 mA37
II = 24 mA37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74CBTLV16292
(INPUT)
(OUTPUT)
LOW-VOLTAGE 12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
SCDS055G – MARCH 1998 – REVISED APRIL 1999
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
PARAMETER
†
t
pd
‡
t
pd
t
en
t
†
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance when
driven by an ideal voltage source (zero output impedance).
‡
This propagation delay was measured by observing the change of voltage on the A output introduced by static levels equal to 3-V or 0 for
3.3 V ± 0.3 V or VCC or 0 for 2.5 V ± 0.2 V on B1 and B2 to achieve the desired transition.
dis
FROM
A or BB or A0.150.15ns
SA2.57.12.56.7ns
SB15.615ns
SB1514.5ns
TO
VCC = 2.5 V
± 0.2 V
MINMAXMINMAX
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
VCC = 2.5 V
PARAMETERDESCRIPTION
§
t
§
The make-before-break time is the time interval between make and break, during the transition from one selected port to the other.
mbb
Make-before-break time0202ns
± 0.2 V
MINMAXMINMAX
VCC = 3.3 V
± 0.3 V
VCC = 3.3 V
± 0.3 V
UNIT
UNIT
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTLV16292
LOW-VOLTAGE 12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
SCDS055G – MARCH 1998 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.5 V ± 0.2 V
CC
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
VCC/2VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
and t
PLZ
PZL
PLH
and t
and t
PHZ
PZH
PHL
500 Ω
500 Ω
VCC/2VCC/2
are the same as t
are the same as ten.
are the same as tpd.
S1
dis
.
t
PHL
2 × V
Open
GND
V
0 V
V
V
CC
CC
OH
OL
Output
Control
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TESTS1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/3
VCC/3
Open
2 × V
GND
CC
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
V
CC
0 V
2 × VCC/3
V
OL
V
OH
0 V
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74CBTLV16292
LOW-VOLTAGE 12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
SCDS055G – MARCH 1998 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
V
= 3.3 V ± 0.3 V
CC
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
1.5 V1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
and t
PLZ
PZL
PLH
and t
and t
PHZ
PZH
PHL
500 Ω
500 Ω
1.5 V1.5 V
are the same as t
are the same as ten.
are the same as tpd.
dis
.
S1
t
PHL
6 V
Open
GND
3 V
0 V
V
OH
V
OL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TESTS1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
1 V
1 V
t
PLZ
t
PHZ
Open
6 V
GND
1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
2 V
V
V
0 V
OL
OH
Figure 2. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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