Datasheet SN74CBTLV16212DL, SN74CBTLV16212DLR, SN74CBTLV16212GR, SN74CBTLV16212VR Datasheet (Texas Instruments)
SN74CBTLV16212
LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH
SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999
D
4-Ω Switch Connection Between Two Ports
D
Isolation Under Power-Off Conditions
D
Break-Before-Make Feature
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and 300-mil Shrink
Small-Outline (DL) Packages
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR, and
the DGVR package is abbreviated to VR.
description
The SN74CBTLV16212 provides 24 bits of
high-speed bus switching or exchanging. The low
on-state resistance of the switch allows
connections to be made with minimal propagation
delay .
The device operates as a 24-bit bus switch or a
12-bit bus exchanger, which provides data
exchanging between the four signal ports via the
data-select (S0, S1, S2) terminals.
The SN74CBTLV16212 is specified by the
break-before-make feature to have no through
current when switching between B ports.
DGG, DGV, OR DL PACKAGE
S0
1A1
1A2
2A1
2A2
3A1
3A2
GND
4A1
4A2
5A1
5A2
6A1
6A2
7A1
7A2
V
CC
8A1
GND
8A2
9A1
9A2
10A1
10A2
11A1
11A2
12A1
12A2
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
S1
S2
1B1
1B2
2B1
2B2
3B1
GND
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
GND
8B2
9B1
9B2
10B1
10B2
11B1
11B2
12B1
12B2
The SN74CBTLV16212 is characterized for
operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN74CBTLV16212
FUNCTION
LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH
SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999
FUNCTION TABLE
INPUTS
S2 S1 S0 A1 A2
L L L Z Z Disconnect
L LH B1 Z A1 port = B1 port
L HL B2 Z A1 port = B2 port
L HH Z B1 A2 port = B1 port
H LL Z B2 A2 port = B2 port
H LH Z Z Disconnect
H HL B1 B2
H H H B2 B1
INPUTS/OUTPUTS
A1 port = B1 port
A2 port = B2 port
A1 port = B2 port
A2 port = B1 port
2
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logic diagram (positive logic)
SN74CBTLV16212
LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH
SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999
1A1
1A2
12A1
12A2
2
3
27
28
SW
SW
SW
SW
SW
SW
SW
SW
54
53
30
29
1B1
1B2
12B1
12B2
S0
S1
S2
1
56
55
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3
SN74CBTLV16212
VIHHigh-level control input voltage
V
VILLow-level control input voltage
V
LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH
SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999
simplified schematic, each FET switch
A
(OE)
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Package thermal impedance, θJA (see Note 2): DGG package) 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
DGV package) 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package) 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
T
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2.3 3.6 V
CC
p
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 2.3 V to 2.7 V 1.7
VCC = 2.7 V to 3.6 V 2
VCC = 2.3 V to 2.7 V 0.7
VCC = 2.7 V to 3.6 V 0.8
4
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V
V
0
TYP at V
CC
V
§
Ω
V
0
(INPUT)
(OUTPUT)
SN74CBTLV16212
LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH
SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
I
I
I
off
I
CC
‡
∆I
C
C
r
on
†
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
‡
This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
§
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
Control inputs VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND 300 µA
CC
Control inputs VI = 3 V or 0 5 pF
i
io(OFF)
VCC = 3 V, II = –18 mA –1.2 V
VCC = 3.6 V, VI = VCC or GND ±1 µA
VCC = 0, VI or VO= 0 to 3.6 V 10 µA
VCC = 3.6 V, IO = 0, VI = VCC or GND 10 µA
VO = 3 V or 0, OE = V
= 2.3 V,
CC
VCC = 3 V
= 2.5
=
=
I
VI = 1.7 V, II = 15 mA 27 40
=
I
VI = 2.4 V, II = 15 mA 10 15
CC
II = 64 mA 5 8
II = 24 mA 5 8
II = 64 mA 5 7
II = 24 mA 5 7
8 pF
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
PARAMETER
¶
t
pd
t
pd
t
en
t
¶
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
dis
FROM
A or B B or A 0.15 0.25 ns
S B or A 3 11.1 3 8.8 ns
S A or B 3 10.9 3 8.6 ns
S A or B 1 8.7 2 8.8 ns
TO
VCC = 2.5 V
± 0.2 V
MIN MAX MIN MAX
VCC = 3.3 V
± 0.3 V
UNIT
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SN74CBTLV16212
LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH
SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
GND
From Output
Under Test
CL = 30 pF
(see Note A)
500 Ω
500 Ω
LOAD CIRCUIT
S1
Output
Control
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
VCC/2VCC/2
V
0 V
CC
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
VCC/2 VCC/2
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 1. Load Circuit and Voltage Waveforms
t
PHL
V
0 V
V
V
CC
OH
OL
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
V
V
V
0 V
CC
OL
OH
6
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SN74CBTLV16212
LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH
SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999
PARAMETER MEASUREMENT INFORMATION
= 3.3 V ± 0.3 V
V
CC
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
and t
PLZ
PZL
PLH
and t
and t
PHZ
PZH
PHL
500 Ω
500 Ω
1.5 V 1.5 V
are the same as t
are the same as ten.
are the same as tpd.
dis
.
S1
t
PHL
6 V
Open
GND
3 V
0 V
V
OH
V
OL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
PLZ
1.5 V
t
PHZ
1.5 V
Open
6 V
GND
1.5 V1.5 V
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
V
V
0 V
OL
OH
Figure 2. Load Circuit and Voltage Waveforms
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7
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