Datasheet SN74CBTLV16211DL, SN74CBTLV16211DLR, SN74CBTLV16211GR, SN74CBTLV16211VR Datasheet (Texas Instruments)

SN74CBTLV16211

LOW-VOLTAGE 24-BIT FET BUS SWITCH

SCDS043E – DECEMBER 1997 – REVISED APRIL 1999

D

5-Ω Switch Connection Between Two Ports

D

Isolation Under Power-Off Conditions

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and 300-mil Shrink
Small-Outline (DL) Packages

description

The SN74CBTLV16211 provides 24 bits of
high-speed bus switching. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay.

The device is organized as dual 12-bit bus
switches with separate output-enable (OE
inputs. It can be used as two 12-bit bus switches
or one 24-bit bus switch. When OE
associated 12-bit bus switch is on and port A is
connected to port B. When OE
is open, and the high-impedance state exists
between the two ports.

T o ensure the high-impedance state during power
up or power down, OE
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.

The SN74CBTLV16211 is characterized for
operation from –40°C to 85°C.

is high, the switch

should be tied to V

is low, the

CC

DGG, DGV, OR DL PACKAGE

)

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

1OE
2OE
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
1B9
1B10
1B1 1
1B12
2B1
2B2
2B3
GND
2B4
2B5
2B6
2B7
2B8
2B9
2B10
2B1 1
2B12

NC
1A1
1A2
1A3
1A4
1A5
1A6

GND

1A7
1A8
1A9

1A10

1A1 1

1A12

2A1
2A2

V

CC

2A3

GND

2A4
2A5
2A6
2A7
2A8
2A9

2A10

2A1 1

2A12

NC – No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

FUNCTION TABLE

(each 12-bit bus switch)
INPUT

OE

L A port = B port

H Disconnect

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION

Copyright  1999, Texas Instruments Incorporated

1

SN74CBTLV16211
LOW-VOLTAGE 24-BIT FET BUS SWITCH

SCDS043E – DECEMBER 1997 – REVISED APRIL 1999

logic diagram (positive logic)

2

1A1

14

1A12

56

1OE

15

2A1

28

2A12

55

2OE

simplified schematic, each FET switch

SW

SW

SW

SW

54

42

41

29

1B1

1B12

2B1

2B12

A

(OE)

B

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I
Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DGV package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

†

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VIHHigh-level control input voltage

V

VILLow-level control input voltage

V

V

2.3 V

V

0

TYP at V

CC

V

§

Ω

V

0

(INPUT)

(OUTPUT)

SN74CBTLV16211

LOW-VOLTAGE 24-BIT FET BUS SWITCH

SCDS043E – DECEMBER 1997 – REVISED APRIL 1999

recommended operating conditions (see Note 3)

MIN MAX UNIT

V

T

NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

V
I

I

I

off

I

CC

∆I
C
C

r

on

†

All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.

‡

This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.

§

Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.

Supply voltage 2.3 3.6 V

CC

p

p

Operating free-air temperature –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

IK

‡

Control inputs VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND 300 µA

CC

Control inputs VI = 3.3 V or 0 4.5 pF

i
io(OFF)

VCC = 3 V, II = –18 mA –1.2 V
VCC = 3.6 V, VI = VCC or GND ±1 µA
VCC = 0, VI or VO= 0 to 3.6 V 10 µA
VCC = 3.6 V, IO = 0, VI = VCC or GND 10 µA

VO = 3.3 V or 0, OE = V

,

=

CC

VCC = 3 V

= 2.5

=

, literature number SCBA004.

CC

=

I

VI = 1.7 V, II = 15 mA 27 40

=

I

VI = 2.4 V, II = 15 mA 10 15

II = 64 mA 5 8
II = 24 mA 5 8

II = 64 mA 5 7
II = 24 mA 5 7

VCC = 2.3 V to 2.7 V 1.7
VCC = 2.7 V to 3.6 V 2
VCC = 2.3 V to 2.7 V 0.7
VCC = 2.7 V to 3.6 V 0.8

6.5 pF

switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)

PARAMETER

¶

The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).

FROM

¶

t

pd

t

en

t

dis

A or B B or A 0.15 0.25 ns

OE A or B 1 7 1 6.2 ns
OE A or B 1 7.2 1 7.7 ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TO

VCC = 2.5 V

± 0.2 V

MIN MAX MIN MAX

VCC = 3.3 V

± 0.3 V

UNIT

3

SN74CBTLV16211
LOW-VOLTAGE 24-BIT FET BUS SWITCH

SCDS043E – DECEMBER 1997 – REVISED APRIL 1999

PARAMETER MEASUREMENT INFORMATION

V

CC

= 2.5 V ± 0.2 V

dis

S1

.

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t

G. t

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

PLZ
PZL
PLH

and t
and t

and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PHL

500 Ω

500 Ω

VCC/2 VCC/2

t

PHL

2 × V

Open

GND

V

0 V

V

V

CC

CC

OH

OL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

VCC/2

Open

2 × V

GND

CC

VCC/2VCC/2

t

PLZ

VOL + 0.15 V

t

PHZ

VOH – 0.15 V

V

0 V

V

V

V

0 V

CC

CC

OL

OH

Figure 1. Load Circuit and Voltage Waveforms

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74CBTLV16211

LOW-VOLTAGE 24-BIT FET BUS SWITCH

SCDS043E – DECEMBER 1997 – REVISED APRIL 1999

PARAMETER MEASUREMENT INFORMATION

V

= 3.3 V ± 0.3 V

CC

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t

F. t

G. t

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

and t

PLZ
PZL
PLH

and t

and t

PHZ
PZH

PHL

500 Ω

500 Ω

1.5 V 1.5 V

are the same as t
are the same as ten.

are the same as tpd.

dis

.

S1

t

PHL

6 V

Open

GND

3 V

0 V

V

OH

V

OL

Output

Control
(low-level
enabling)

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

t

PZL

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

t

PLZ

1.5 V

t

PHZ

1.5 V

Open

6 V

GND

1.5 V1.5 V

VOL + 0.3 V

VOH – 0.3 V

3 V

0 V

3 V

V

V

0 V

OL

OH

Figure 2. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

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Copyright  1999, Texas Instruments Incorporated