Texas Instruments SN74CBTD16211DGGR, SN74CBTD16211DGVR, SN74CBTD16211DL, SN74CBTD16211DLR Datasheet
SN74CBTD16211
24-BIT FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS048C – MARCH 1998 – REVISED MA Y 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
5-Ω Switch Connection Between Two Ports
D
TTL-Compatible Input Levels
D
Designed to Be Used in Level-Shifting
Applications
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
description
The SN74CBTD16211 provides 24 bits of
high-speed TTL-compatible bus switching. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
delay . A diode to V
CC
is integrated in the circuit to
allow for level shifting between 5-V inputs and
3.3-V outputs.
The device is organized as a dual 12-bit bus
switch with separate output-enable (OE
) inputs. It
can be used as two 12-bit bus switches or as one
24-bit bus switch. When OE
is low, the associated
12-bit bus switch is on and A port is connected to
B port. When OE
is high, the switch is open, and
a high-impedance state exists between the ports.
The SN74CBTD16211 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(each 12-bit bus switch)
INPUT
OE
FUNCTION
L A port = B port
H Disconnect
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
1A1
1A2
1A3
1A4
1A5
1A6
GND
1A7
1A8
1A9
1A10
1A1 1
1A12
2A1
2A2
V
CC
2A3
GND
2A4
2A5
2A6
2A7
2A8
2A9
2A10
2A1 1
2A12
1OE
2OE
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
1B9
1B10
1B1 1
1B12
2B1
2B2
2B3
GND
2B4
2B5
2B6
2B7
2B8
2B9
2B10
2B1 1
2B12
NC – No internal connection
SN74CBTD16211
24-BIT FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS048C – MARCH 1998 – REVISED MA Y 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1A1
1A12
1OE
1B1
1B12
2A1
2A12
2OE
2B1
2B12
2
14
56
15
28
55
54
42
41
29
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
Supply voltage 4.5 5.5 V
V
IH
High-level control input voltage 2 V
V
IL
Low-level control input voltage 0.8 V
T
A
Operating free-air temperature –40 85 °C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
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