Texas Instruments SN74CBT3384ADBLE, SN74CBT3384ADBQR, SN74CBT3384ADBR, SN74CBT3384ADGVR, SN74CBT3384ADW Datasheet

SN74CBT3384A

10-BIT FET BUS SWITCH

SCDS004I – NOVEMBER 1992 – REVISED MA Y 1998

D

Functionally Equivalent to QS3384 and

DB, DBQ, DGV, DW, OR PW PACKAGE

QS3L384

D

5-Ω Switch Connection Between Two Ports

D

TTL-Compatible Input Levels

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB, DBQ), Thin Very Small-Outline (DGV),
and Thin Shrink Small-Outline (PW)
Packages

description

The SN74CBT3384A provides ten bits of
high-speed TTL-compatible bus switching. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
delay .

The device is organized as two 5-bit switches with separate output-enable (OE
switch is on and port A is connected to port B. When OE
exists between the two ports.

The SN74CBT3384A is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each 5-bit bus switch)

INPUTS

1OE 2OE 1B1–1B5 2B1–2B5

L L 1A1–1A5 2A1–2A5

L H 1A1–1A5 Z
H LZ2A1–2A5
H H Z Z

is high, the switch is open and a high-impedance state

INPUTS/OUTPUTS

1OE

1B1
1A1
1A2
1B2
1B3
1A3
1A4
1B4
1B5
1A5

GND

(TOP VIEW)

24
23
22
21
20
19
18
17
16
15
14
13

V

CC

2B5
2A5
2A4
2B4
2B3
2A3
2A2
2B2
2B1
2A1
2OE

1
2
3
4
5
6
7
8
9
10
11
12

) inputs. When OE is low, the

logic diagram (positive logic)

1OE

2OE

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

32

1A1

11

1A5

1

14 15

2A1

22

2A5

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

10

23

1B1

1B5

2B1

2B5

Copyright  1998, Texas Instruments Incorporated

1

SN74CBT3384A

¶

on

V

0

10-BIT FET BUS SWITCH

SCDS004I – NOVEMBER 1992 – REVISED MA Y 1998

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

†

Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I
Package thermal impedance, θ

IK

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O

(see Note 2): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DBQ package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 139°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 3)

MIN MAX UNIT

V
V
V
T

NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 4 5.5 V

CC

High-level control input voltage 2 V

IH

Low-level control input voltage 0.8 V

IL

Operating free-air temperature –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

V

IK

I

I

I

CC

§

∆I

CC

C

i

C

io(OFF)

r

n

‡

All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.

§

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

¶

Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lowest voltage of the two (A or B) terminals.

Control inputs VCC = 5.5 V, One input at 3.4 V , Other inputs at VCC or GND 2.5 mA
Control inputs VI = 3 V or 0 4 pF

VCC = 4.5 V, II = –18 mA –1.2 V
VCC = 5.5 V, VI = 5.5 V or GND ±1 µA
VCC = 5.5 V, IO = 0, VI = VCC or GND 3 µA

VO = 3 V or 0, OE = V
VCC = 4 V,

TYP at VCC = 4 V

VCC = 4.5 V

VI = 2.4 V, II = 15 mA 14 20

=

I

VI = 2.4 V, II = 15 mA 10 15

CC

II = 64 mA 5 7
II = 30 mA 5 7

4.5 pF

Ω

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(INPUT)

(OUTPUT)

SN74CBT3384A

10-BIT FET BUS SWITCH

SCDS004I – NOVEMBER 1992 – REVISED MA Y 1998

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)

PARAMETER

†

t

pd

t

en

t

dis

†

The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).

FROM

A or B B or A 0.35 0.25 ns

OE
OE

TO

A or B 6.2 1.9 5.7 ns
A or B 5.5 2.1 5.2 ns

VCC = 4 V
MIN MAX MIN MAX

PARAMETER MEASUREMENT INFORMATION

VCC = 5 V

± 0.5 V

UNIT

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t

G. t

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

and t

PLZ
PZL
PLH

and t

and t

PHZ
PZH

PHL

500 Ω

500 Ω

1.5 V 1.5 V

are the same as t
are the same as ten.

are the same as tpd.

dis

.

S1

t

PHL

7 V

Open

GND

3 V

0 V

V

OH

V

OL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

t

PZL

1.5 V

t

PZH

1.5 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

t

PLZ

t

PHZ

Open

7 V

Open

1.5 V1.5 V

VOL + 0.3 V

VOH – 0.3 V

3 V

0 V

3.5 V

V

OL

V

OH

0 V

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

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Copyright  1998, Texas Instruments Incorporated