Texas Instruments SN74CBT3345DGVR, SN74CBT3345DW, SN74CBT3345DWR, SN74CBT3345PWLE, SN74CBT3345PWR Datasheet
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SN74CBT3345
8-BIT FET BUS SWITCH
SCDS027D – MAY 1995 – REVISED MAY 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Standard ’245-Type Pinout
D
5-Ω Switch Connection Between Two Ports
D
TTL-Compatible Input Levels
D
Package Options Include Plastic Shrink
Small-Outline (DB), Thin Very Small-Outline
(DGV), Small-Outline (DW), and Thin Shrink
Small-Outline (PW) Packages
description
The SN74CBT3345 provides eight bits of
high-speed TTL-compatible bus switching in a
standard ’245 device pinout. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay.
The device is organized as one 8-bit switch bank with dual output-enable (OE and OE
) inputs. When OE is low
or OE is high, the switch is on and port A is connected to port B. When OE
is high and OE is low, the switch is
open and a high-impedance state exists between the two ports.
The SN74CBT3345 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUT
OE
FUNCTION
L A port = B port
H Disconnect
logic diagram (positive logic)
A1
A8
OE
B1
B8
OE
2
9
1
19
18
11
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1998, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
DB, DGV, DW, OR PW PACKAGE
(TOP VIEW)
SN74CBT3345
8-BIT FET BUS SWITCH
SCDS027D – MAY 1995 – REVISED MAY 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I/O
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DB package 115°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 146°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 97°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
Supply voltage 4.5 5.5 V
V
IH
High-level control input voltage 2 V
V
IL
Low-level control input voltage 0.8 V
T
A
Operating free-air temperature 0 70 °C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 V
I
I
VCC = 5.5 V, VI = 5.5 V or GND ±1 µA
I
CC
VCC = 5.5 V, IO = 0, VI = VCC or GND 50 µA
∆I
CC
§
Control inputs VCC = 5.5 V, One input at 3.4 V , Other inputs at VCC or GND 3.5 mA
C
i
Control inputs VI = 3 V or 0 3 pF
C
io(OFF)
VO = 3 V or 0, OE = VCC or OE = GND 6 pF
II = 64 mA 5 7
r
on
¶
VCC = 4.5 V
V
I
=
0
II = 30 mA 5 7
Ω
VI = 2.4 V, II = 15 mA 10 15
‡
All typical values are at VCC = 5 V, TA = 25°C.
§
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
¶
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
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