Texas Instruments SN74CBT3253D, SN74CBT3253DBLE, SN74CBT3253DBQR, SN74CBT3253DBR, SN74CBT3253DR Datasheet
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FUNCTION
SN74CBT3253
DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
SCDS018I – MAY 1995 – REVISED MAY 1998
D
Functionally Equivalent to QS3253
D
5-Ω Switch Connection Between Two Ports
D
TTL-Compatible Input Levels
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB, DBQ), Thin Very Small-Outline (DGV),
and Thin Shrink Small-Outline (PW)
Packages
description
The SN74CBT3253 is a dual 1-of-4 high-speed
TTL-compatible FET multiplexer/demultiplexer.
The low on-state resistance of the switch allows
connections to be made with minimal propagation
delay .
1OE
, 2OE, S0, and S1 select the appropriate
B output for the A-input data.
The SN74CBT3253 is characterized for operation
from –40°C to 85°C.
FUNCTION TABLE
(each multiplexer/demultiplexer)
INPUTS
OE
S1 S0
L L L A port = B1 port
L L H A port = B2 port
L H L A port = B3 port
L H H A port = B4 port
H X X Disconnect
D, DB, DBQ, DGV, OR PW PACKAGE
1OE
S1
1B4
1B3
1B2
1B1
1A
GND
(TOP VIEW)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
V
CC
2OE
S0
2B4
2B3
2B2
2B1
2A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
SN74CBT3253
DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
SCDS018I – MAY 1995 – REVISED MAY 1998
logic diagram (positive logic)
S0
S1
14
2
1A
2A
10
11
12
13
6
1B1
5
1B2
4
1B3
3
1B4
2B1
2B2
2B3
2B4
7
9
1
1OE
15
2OE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O
(see Note 2): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
K
DB package 131°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DBQ package 139°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 180°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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