Texas Instruments SN74CBT3244DBLE, SN74CBT3244DBQR, SN74CBT3244DBR, SN74CBT3244DGVR, SN74CBT3244DW Datasheet

SN74CBT3244

OCTAL FET BUS SWITCH

SCDS001H – NOVEMBER 1992 – REVISED MA Y 1998

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Functionally Equivalent to QS3244

D

Standard ’244-Type Pinout

D

5-Ω Switch Connection Between Two Ports

D

TTL-Compatible Input Levels

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB, DBQ), Thin Very Small-Outline (DGV),
and Thin Shrink Small-Outline (PW)
Packages

description

The SN74CBT3244 provides eight bits of
high-speed TTL-compatible bus switching in a
standard ’244 device pinout. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay.

The device is organized as two 4-bit low-impedance switches with separate output-enable (OE

) inputs. When

OE

is low, the switch is on and data can flow from port A to port B, or vice versa. When OE is high, the switch

is open and a high-impedance state exists between the two ports.
The SN74CBT3244 is characterized for operation from 0°C to 70 °C.

FUNCTION TABLE

(each 4-bit bus switch)

INPUT

OE

FUNCTION

L A port = B port
H Disconnect

logic diagram (positive logic)

1OE

1A1

1A4

1B1

1B4

2

8

1

18

12

2OE

2A1

2A4

2B1

2B4

11

17

19

9

3

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1998, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

1OE

1A1
2B4
1A2
2B3
1A3
2B2
1A4
2B1

GND

V

CC

2OE
1B1
2A4
1B2
2A3
1B3
2A2
1B4
2A1

DB, DBQ, DGV, DW, OR PW PACKAGE

(TOP VIEW)

SN74CBT3244
OCTAL FET BUS SWITCH

SCDS001H – NOVEMBER 1992 – REVISED MA Y 1998

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clamp current, I

K

(V

I/O

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 2): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DBQ package 118°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 146°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 3)

MIN MAX UNIT

V

CC

Supply voltage 4.5 5.5 V

V

IH

High-level control input voltage 2 V

V

IL

Low-level control input voltage 0.8 V

T

A

Operating free-air temperature 0 70 °C

NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

V

IK

VCC = 4.5 V, II = –18 mA –1.2 V

I

I

VCC = 5.5 V, VI = 5.5 V or GND ±5 µA

I

CC

VCC = 5.5 V, IO = 0, VI = VCC or GND 50 µA

∆I

CC

§

Control inputs VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 3.5 mA

C

i

Control inputs VI = 3 V or 0 3 pF

C

io(OFF)

VO = 3 V or 0, OE = V

CC

6 pF

II = 64 mA 5 7

r

on

¶

VCC = 4.5 V

V

I

=

0

II = 30 mA 5 7

Ω

VI = 2.4 V, II = 15 mA 10 15

‡

All typical values are at VCC = 5 V, TA = 25°C.

§

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

¶

Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined
by the lowest voltage of the two (A or B) terminals.

SN74CBT3244

OCTAL FET BUS SWITCH

SCDS001H – NOVEMBER 1992 – REVISED MA Y 1998

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

MIN MAX UNIT

t

pd

†

A or B B or A 0.25 ns

t

en

OE

A or B 1 8.9 ns

t

dis

OE

A or B 1 7.4 ns

†

This propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).

PARAMETER MEASUREMENT INFORMATION

V

OH

V

OL

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

7 V

Open

GND

500 Ω

500 Ω

t

PLH

t

PHL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

t

PZL

t

PZH

t

PLZ

t

PHZ

1.5 V1.5 V

1.5 V 1.5 V

3 V

0 V

1.5 V 1.5 V

V

OH

V

OL

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH – 0.3 V

0 V

Input

3 V

3.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Output

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

Open

7 V

Open

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

E. t

PLZ

and t

PHZ

are the same as t

dis

.

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

andt

PHL

are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

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Copyright  1998, Texas Instruments Incorporated