Texas Instruments SN74CBT3126DBQR, SN74CBT3126DBR, SN74CBT3126DGVR, SN74CBT3126DR, SN74CBT3126PWR Datasheet

SN74CBT3126

QUADRUPLE FET BUS SWITCH

SCDS020E – MAY 1995 – REVISED MAY 1998

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Standard ’126-Type Pinout (D, DGV, and PW
Packages)

D

5-Ω Switch Connection Between Two Ports

D

TTL-Compatible Input Levels

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DBQ), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages

description

The SN74CBT3126 quadruple FET bus switch
features independent line switches. Each switch
is disabled when the associated output-enable
(OE) input is low.

The SN74CBT3126 is characterized for operation
from –40°C to 85°C.

FUNCTION TABLE

(each bus switch)

INPUT

OE

FUNCTION

L Disconnect
H A = B

logic diagram (positive logic)

1OE

1B

1A

2OE

2B

2A

3OE

3B

3A

4OE

4B

4A

Pin numbers shown are for the D, DGV, and PW packages.

2

1

5

4

9

10

12

13

3

6

8

11

1
2
3
4
5
6
7

14
13
12
11
10

9
8

1OE

1A
1B

2OE

2A
2B

GND

V

CC

4OE
4A
4B
3OE
3A
3B

D, DGV, OR PW PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

NC

1OE

1A
1B

2OE

2A
2B

GND

V

CC

4OE
4A
4B
3OE
3A
3B
NC

DBQ PACKAGE

(TOP VIEW)

NC – No internal connection

Copyright  1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN74CBT3126
QUADRUPLE FET BUS SWITCH

SCDS020E – MAY 1995 – REVISED MAY 1998

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

K

(V

I/O

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DBQ package 139°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 182°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 3)

MIN MAX UNIT

V

CC

Supply voltage 4 5.5 V

V

IH

High-level control input voltage 2 V

V

IL

Low-level control input voltage 0.8 V

T

A

Operating free-air temperature –40 85 °C

NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

V

IK

VCC = 4 V, II = –18 mA –1.2 V

I

I

VCC = 5.5 V, VI = 5.5 V or GND ±1 µA

I

CC

VCC = 5.5 V, IO = 0, VI = VCC or GND 3 µA

∆I

CC

§

Control inputs VCC = 5.5 V, One input at 3.4 V , Other inputs at VCC or GND 2.5 mA

C

i

Control inputs VI = 3 V or 0 3 pF

C

io(OFF)

VO = 3 V or 0, OE = GND 4 pF
VCC = 4 V, TYP at VCC = 4 V, VI = 2.4 V, II = 15 mA 16 22

II = 64 mA 5 7

r

on

¶

VCC = 4.5 V

V

I

=

0

II = 30 mA 5 7

Ω

VI = 2.4 V, II = 15 mA 10 15

‡

All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.

§

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

¶

Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined
by the lower of the voltages of the two (A or B) terminals.