Datasheet SN74CBT16244DGGR, SN74CBT16244DGVR, SN74CBT16244DLR, SNJ54CBT16244WD Datasheet (Texas Instruments)

SN54CBT16244, SN74CBT16244

16-BIT FET BUS SWITCHES

SCDS031G – MAY 1996 – REVISED SEPTEMBER 1998

D

Standard ’16244-Type Pinout

D

5-Ω Switch Connection Between Two Ports

D

TTL-Compatible Input Levels

D

Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and Shrink
Small-Outline (DL) Packages, and Ceramic
Flat (WD) Package

description

The ’CBT16244 devices provide 16 bits of
high-speed TTL-compatible bus switching in a
standard ’16244 device pinout. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay.

These devices are organized as four 4-bit
low-impedance switches with separate
output-enable (OE
switch is on and data can flow from port A to port
B, or vice versa. When OE
open and a high-impedance state exists between
the two ports.

The SN54CBT16244 is characterized for
operation over the full military temperature range
of –55°C to 125°C. The SN74CBT16244 is
characterized for operation from –40°C to 85°C.

) inputs. When OE is low, the

is high, the switch is

SN54CBT16244 . . . WD PACKAGE

SN74CBT16244 . . . DGG, DGV, OR DL PACKAGE

1OE

1B1
1B2

GND

1B3
1B4

V

CC

2B1
2B2

GND

2B3
2B4
3B1
3B2

GND

3B3
3B4

V

CC

4B1
4B2

GND

4B3
4B4

4OE

(TOP VIEW)

1

48

2

47

3

46

4

45

5

44

6

43

7

42

8

41

9

40

10

39

11

38

12

37

13

36

14

35

15

34

16

33

17

32

18

31

19

30

20

29

21

28

22

27

23

26

24

25

2OE
1A1
1A2
GND
1A3
1A4
V

CC

2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
V

CC

4A1
4A2
GND
4A3
4A4
3OE

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

FUNCTION TABLE

(each 4-bit bus switch)

INPUT

OE

L A port = B port

H Z

OUTPUTS

A, B

Copyright  1998, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54CBT16244, SN74CBT16244

UNIT

16-BIT FET BUS SWITCHES

SCDS031G – MAY 1996 – REVISED SEPTEMBER 1998

logic diagram (positive logic)

13

17

2

1B1

6

1B4

3B1

3B4

47

1A1

43

1A4

1

1OE

36

3A1

32

3A4

25

3OE

Pin numbers shown are for the DGG, DGV, and DL packages.

41

2A1

37

2A4

48

2OE

30

4A1 4B1

26

4A4

24

4OE

12

19

23

8

2B1

2B4

4B4

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I
Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O

(see Note 2): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

IK

DGV package 93°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

†

recommended operating conditions (see Note 3)

SN54CBT16244 SN74CBT16244

MIN MAX MIN MAX

V
V
V
T

NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

2

Supply voltage 4 5.5 4 5.5 V

CC

High-level control input voltage 2 2 V

IH

Low-level control input voltage 0.8 0.8 V

IL

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

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PARAMETER

TEST CONDITIONS

UNIT

I

A

r

§

Ω

SN54CBT16244, SN74CBT16244

16-BIT FET BUS SWITCHES

SCDS031G – MAY 1996 – REVISED SEPTEMBER 1998

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54CBT16244 SN74CBT16244

MIN TYP†MAX MIN TYP†MAX

V

IK

I

I

CC

Control

‡

∆I

CC

inputs

i
io(OFF)

Control
inputs

C
C

on

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

§

Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.

VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 0 VI = 5.5 V 10 10
VCC = 5.5 V VI = 5.5 V or GND ±1 ±1
VCC = 5.5 V,

VI = VCC or GND
VCC = 5.5 V,

Other inputs at VCC or GND
VI = 3 V or 0 2.5 2.5 pF
VO = 3 V or 0, OE = V

VCC = 4 V, VI = 2.4 V, II = 15 mA 20 20

VCC = 4.5 V

IO = 0,

One input at 3.4 V ,

CC

VI = 0, II = 64 mA 5 10 5 7
VI = 0, II = 30 mA 5 10 5 7
VI = 2.4 V, II = 15 mA 8 14 8 12

3.2 3 µA

2.5 2.5 mA

4.5 4.5 pF

µ

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)

SN54CBT16244 SN74CBT16244

PARAMETER

¶

t

pd

t

en

t

dis

* On products compliant to MIL-PRF-38535, this parameter is not production tested.
¶

The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).

FROM

(INPUT)

A or B B or A 0.8* 0.35 0.25 ns

OE
OE

TO

(OUTPUT)

A or B 10.3 1 9.2 5.5 1 5.1 ns
A or B 9.7 1 8.2 5.2 1 5.4 ns

VCC = 4 V
MIN MAX MIN MAX MIN MAX MIN MAX

VCC = 5 V

± 0.5 V

VCC = 4 V

VCC = 5 V

± 0.5 V

UNIT

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3

SN54CBT16244, SN74CBT16244
16-BIT FET BUS SWITCHES

SCDS031G – MAY 1996 – REVISED SEPTEMBER 1998

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t

F. t

G. t

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

and t

PLZ
PZL
PLH

and t

and t

PHZ
PZH

PHL

500 Ω

500 Ω

1.5 V 1.5 V

are the same as t
are the same as ten.
are the same as tpd.

dis

.

S1

t

PHL

7 V

GND

3 V

0 V

V

OH

V

OL

Open

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

t

PZL

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

t

PLZ

1.5 V

t

PHZ

1.5 V

Open

7 V

Open

1.5 V1.5 V

VOL + 0.3 V

VOH – 0.3 V

3 V

0 V

3.5 V

V

OL

V

OH

0 V

Figure 1. Load Circuit and Voltage Waveforms

4

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Copyright  1998, Texas Instruments Incorporated