Datasheet SN74CBT16233DGGR, SN74CBT16233DGVR, SN74CBT16233DL, SN74CBT16233DLR Datasheet (Texas Instruments)
FUNCTION
SN74CBT16233
16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS010H – MA Y 1995 – REVISED OCT OBER 1998
D
5-Ω Switch Connection Between Two Ports
D
TTL-Compatible Input Levels
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and 300-mil Shrink
Small-Outline (DL) Packages
description
The SN74CBT16233 is a 16-bit 1-of-2 FET
multiplexer/demultiplexer used in applications in
which two separate data paths must be
multiplexed onto, or demultiplexed from, a single
path. This device can be used for memory
interleaving, where two different banks of memory
need to be addressed simultaneously . The device
can be used as two 8-bit to 16-bit multiplexers or
as one 16-bit to 32-bit multiplexer.
Two select (SEL1 and SEL2) inputs control the
data flow. When the TEST inputs are asserted, the
A port is connected to both the B1 and the B2
ports. SEL1, SEL2, and the TEST inputs can be
driven with a 5-V CMOS, a 5-V TTL, or a
low-voltage TTL driver.
The device is specified by design not to have
through current when switching directions.
The SN74CBT16233 is characterized for
operation from 0°C to 70°C.
DGG, DGV, OR DL PACKAGE
TEST1
TEST2
1A
2B1
2B2
3A
4B1
4B2
5A
6B1
6B2
7A
8B1
8B2
GND
V
CC
9A
10B1
10B2
11A
12B1
12B2
13A
14B1
14B2
15A
16B1
16B2
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1B1
1B2
2A
3B1
3B2
4A
5B1
5B2
6A
7B1
7B2
8A
GND
V
CC
9B1
9B2
10A
1 1B1
1 1B2
12A
13B1
13B2
14A
15B1
15B2
16A
SEL1
SEL2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
FUNCTION TABLE
(each multiplexer/demultiplexer)
INPUTS
SEL TEST
L L A = B1
H L A = B2
X H A = B1 and A = B2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
SN74CBT16233
16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS010H – MA Y 1995 – REVISED OCT OBER 1998
logic diagram (positive logic)
1A
8A
SEL1
TEST1
1
45
30
27
56
55
12
15
9A
1B1
1B2
11
8B1
8B2
TEST2
16A
SEL2
31
29
28
42
41
25
26
9B1
9B2
16B1
16B2
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DGV package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
V
V
T
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
2
Supply voltage 4.75 5.25 V
CC
High-level control input voltage 2 V
IH
Low-level control input voltage 0.8 V
IL
Operating free-air temperature 0 70 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I
§
V
0
PARAMETER
MIN
MAX
UNIT
SN74CBT16233
16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS010H – MA Y 1995 – REVISED OCT OBER 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
I
I
CC
‡
∆I
CC
C
i
C
io(OFF)
r
on
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
§
Measured by the voltage drop between A and B terminals at the indicated current through the switch. On-state resistance is determined by the
lower of the voltages of the two (A or B) terminals.
Control inputs VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 2.5 mA
Control inputs VI = 3 V or 0 4.5 pF
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
VCC = 4.75 V, II = –18 mA –1.2 V
VCC = 0, VI = 5.25 V 10 µA
VCC = 5.25 V, VI = 5.25 V or GND ±1 µA
VCC = 5.25 V, IO = 0, VI = VCC or GND 3 µA
VO = 3 V or 0 4 pF
II = 64 mA 5 7
II = 30 mA 5 7
VCC = 4.75 V
=
I
VI = 2.4 V, II = 15 mA 7 12
Ω
FROM TO
(INPUT) (OUTPUT)
¶
t
pd
t
pd
t
en
t
¶
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
dis
A or B B or A 0.25 ns
SEL A 1.6 5.3 ns
TEST or SEL B 1.3 5.2 ns
TEST or SEL B 1 5.3 ns
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3
SN74CBT16233
16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS010H – MA Y 1995 – REVISED OCT OBER 1998
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
and t
PLZ
PZL
PLH
and t
and t
PHZ
PZH
PHL
500 Ω
500 Ω
1.5 V 1.5 V
are the same as t
are the same as ten.
are the same as tpd.
dis
.
S1
t
PHL
7 V
Open
GND
3 V
0 V
V
OH
V
OL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
t
PZL
1.5 V
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
t
PLZ
t
PHZ
1.5 V
Open
7 V
Open
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3.5 V
V
OL
V
OH
0 V
Figure 1. Load Circuit and Voltage Waveforms
4
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