SN74CBT16232
SYNCHRONOUS 16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS009J – MAY 1995 – REVISED MAY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
5-Ω Switch Connection Between Two Ports
D
TTL-Compatible Input and Output Levels
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and 300-mil
Shrink Small-Outline (DL) Packages
description
The SN74CBT16232 is a synchronous 16-bit
1-of-2 FET multiplexer/demultiplexer used in
applications in which two separate data paths
must be multiplexed onto, or demultiplexed from,
a single path.
Two select (S0 and S1) inputs control the data
flow. A clock (CLK) and a clock enable (CLKEN
)
synchronize the device operation. When CLKEN
is high, the bus switch remains in the last clocked
function.
The SN74CBT16232 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
S1 S0 CLK CLKEN
FUNCTION
X X X H Last state
L L ↑ L Disconnect
L H ↑ L A = B1 and A = B2
H L ↑ L A = B1
H H ↑ L A = B2
1B1
1B2
2A
3B1
3B2
4A
5B1
5B2
6A
7B1
7B2
8A
GND
V
CC
9B1
9B2
10A
1 1B1
1 1B2
12A
13B1
13B2
14A
15B1
15B2
16A
S0
S1
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1A
2B1
2B2
3A
4B1
4B2
5A
6B1
6B2
7A
8B1
8B2
GND
V
CC
9A
10B1
10B2
11A
12B1
12B2
13A
14B1
14B2
15A
16B1
16B2
CLK
CLKEN
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, T exas Instruments Incorporated
SN74CBT16232
SYNCHRONOUS 16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS009J – MAY 1995 – REVISED MAY 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1A
S0
S1
CE
CLK
D
CLK
CLKEN
CE
CLK
D
56
55
25
26
1
31
28
27
30
29
16A
1B1
1B2
16B1
16B2
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
Supply voltage 4 5.5 V
V
IH
High-level control input voltage 2 V
V
IL
Low-level control input voltage 0.8 V
T
A
Operating free-air temperature –40 85 °C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
SN74CBT16232
SYNCHRONOUS 16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS009J – MAY 1995 – REVISED MAY 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 V
I
I
VCC = 5.5 V, VI = 5.5 V or GND ±1 µA
I
CC
VCC = 5.5 V, IO = 0, VI = VCC or GND 3 µA
∆I
CC
‡
Control inputs VCC = 5.5 V, One input at 3.4 V , Other inputs at VCC or GND 2.5 mA
C
i
Control inputs VI = 3 V or 0 4.5 pF
A port
6.5
p
C
io(OFF)
B port
V
O
=
3 V or 0
,
CLKEN
= 0,
S0
= 0,
S1
=
0
4
pF
VCC = 4 V,
TYP at VCC = 4 V
VI = 2.4 V, II = 15 mA 14 20
r
§
II = 64 mA 5 7
Ω
on
VCC = 4.5 V
V
I
=
0
II = 30 mA 5 7
VI = 2.4 V, II = 15 mA 10 15
†
All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
‡
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
§
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
VCC = 4 V
VCC = 5 V
± 0.5 V
UNIT
MIN MAX MIN MAX
f
clock
Clock frequency 150 150 MHz
t
w
Pulse duration CLK high or low 3.3 3.3 ns
S0, S1 before CLK↑ 2.2 1.9
t
su
Set
up time
CLKEN
before CLK↑ 2.4 1.9
ns
S0, S1 after CLK↑ 0.5 1
thHold time
CLKEN after CLK↑ 1.9 1.8
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC = 4 V
VCC = 5 V
± 0.5 V
UNIT
(INPUT)
(OUTPUT)
MIN MAX MIN MAX
f
max
150 150 MHz
t
pd
¶
A or B B or A 0.35 0.25 ns
t
pd
CLK A or B 6.1 2 5.8 ns
A, B1, B2 6.8 1.8 6.2
t
en
CLK
B1 and B2 8.5 3.1 7.9
ns
t
dis
CLK
A or B 5.8 1.9 6.2 ns
¶
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
SN74CBT16232
SYNCHRONOUS 16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS009J – MAY 1995 – REVISED MAY 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
OH
V
OL
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
t
PLH
t
PHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V1.5 V
1.5 V 1.5 V
3 V
0 V
1.5 V 1.5 V
V
OH
V
OL
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
0 V
Input
3 V
3.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
7 V
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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intellectual property right of TI covering or relating to any combination, machine, or process in which such
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Copyright 1999, Texas Instruments Incorporated
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