Texas Instruments SN74CBT16232DGGR, SN74CBT16232DL, SN74CBT16232DLR Datasheet

SN74CBT16232
SYNCHRONOUS 16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS009J – MAY 1995 – REVISED MAY 1999
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D
5-Switch Connection Between Two Ports
D
D
Package Options Include Plastic Thin Shrink Small-Outline (DGG) and 300-mil Shrink Small-Outline (DL) Packages
description
The SN74CBT16232 is a synchronous 16-bit 1-of-2 FET multiplexer/demultiplexer used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single path.
Two select (S0 and S1) inputs control the data flow. A clock (CLK) and a clock enable (CLKEN
) synchronize the device operation. When CLKEN is high, the bus switch remains in the last clocked function.
The SN74CBT16232 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
S1 S0 CLK CLKEN
FUNCTION
X X X H Last state L L L Disconnect L H L A = B1 and A = B2 H L L A = B1 H H L A = B2
1B1 1B2 2A 3B1 3B2 4A 5B1 5B2 6A 7B1 7B2 8A GND V
CC
9B1 9B2 10A 1 1B1 1 1B2 12A 13B1 13B2 14A 15B1 15B2 16A S0 S1
DGG OR DL PACKAGE
(TOP VIEW)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1A 2B1 2B2
3A 4B1 4B2
5A 6B1 6B2
7A 8B1 8B2
GND
V
CC
9A
10B1 10B2
11A
12B1 12B2
13A
14B1 14B2
15A
16B1 16B2
CLK
CLKEN
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, T exas Instruments Incorporated
SN74CBT16232 SYNCHRONOUS 16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS009J – MAY 1995 – REVISED MAY 1999
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram (positive logic)
1A
S0
S1
CE
CLK
D
CLK
CLKEN
CE
CLK
D
56
55
25
26
1
31
28
27
30
29
16A
1B1
1B2
16B1
16B2
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
Supply voltage 4 5.5 V
V
IH
High-level control input voltage 2 V
V
IL
Low-level control input voltage 0.8 V
T
A
Operating free-air temperature –40 85 °C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
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