Datasheet SN74CBT162292DGGR, SN74CBT162292DGVR, SN74CBT162292DL, SN74CBT162292DLR Datasheet (Texas Instruments)

SN74CBT162292

12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER

WITH INTERNAL PULLDOWN RESISTORS

SCDS052C – MARCH 1998 – REVISED MA Y 1998

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

TTL-Compatible Control Input Levels

D

Isolation Under Power-Off Conditions

D

Make-Before-Break Feature

D

Internal 500-Ω Pulldown Resistors to
Ground

D

A-Port Inputs/Outputs Have Equivalent
25-Ω Series Resistors, So No External
Resistors Are Required

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and 300-mil Shrink
Small-Outline (DL) Packages

description

The SN74CBT162292 is a 12-bit 1-of-2
high-speed TTL-compatible FET multiplexer/
demultiplexer. The low on-state resistance of the
switch allows connections to be made with
minimal propagation delay.

When the select (S) input is low, port A is
connected to port B1 and R

INT

is connected to port
B2. When S is high, port A is connected to port B2
and R

INT

is connected to port B1.

The A-port inputs/outputs include equivalent 25-Ω
series resistors to reduce overshoot and
undershoot.

The SN74CBT162292 is characterized for
operation from –40°C to 85°C.

FUNCTION TABLE

INPUT

S

FUNCTION

L

A port = B1 port

R

INT

= B2 port

H

A port = B2 port

R

INT

= B1 port

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1998, Texas Instruments Incorporated

DGG, DGV, OR DL PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

S

1A

NC

2A

NC

3A

NC

GND

4A

NC

5A

NC

6A

NC

7A

NC

V

CC

8A

GND

NC

9A

NC

10A

NC

11A

NC

12A

NC

NC
NC
1B1
1B2
2B1
2B2
3B1
GND
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
GND
8B2
9B1
9B2
10B1
10B2
1 1B1
1 1B2
12B1
12B2

NC – No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN74CBT162292
12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS

SCDS052C – MARCH 1998 – REVISED MA Y 1998

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1A 1B1

R

INT

1B2

R

INT

S

12A

12B1

R

INT

12B2

R

INT

2

27

1

54

53

30

29

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(V

I

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

SN74CBT162292

12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER

WITH INTERNAL PULLDOWN RESISTORS

SCDS052C – MARCH 1998 – REVISED MA Y 1998

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 3)

MIN MAX UNIT

V

CC

Supply voltage 4 5.5 V

V

IH

High-level control input voltage 2 V

V

IL

Low-level control input voltage 0.8 V

T

A

Operating free-air temperature –40 85 °C

NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IK

VCC = 4.5 V, II = –18 mA –1.2 V

I

I

VCC = 5.5 V, VI = VCC or GND ±5 µA

I

off

VCC = 0, VI or VO = 0 to 7 V 10 µA

I

CC

VCC = 5.5 V, IO = 0, VI = VCC or GND 3 µA

∆I

CC

‡

Control input VCC = 5.5 V, One input at 3.4 V , Other inputs at VCC or GND 2.5 mA

C

i

Control input VI = 3 V or 0 3.5 pF

C

io

VCC = 0, VO = 3 V or 0 8 pF
VCC = 4 V,

TYP at VCC = 4 V

VI = 2.4 V, II = 15 mA 38 55

r

§

II = 45 mA 39 63

Ω

on

VCC = 4.5 V

V

I

=

0

II = 30 mA 37 55

VI = 2.4 V, II = 15 mA 37 55

†

All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.

‡

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

§

Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.

switching characteristics over recommended operating free-air temperature range, CL = 50 pF,
(unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

VCC = 4 V

VCC = 5 V

± 0.5 V

UNIT

(INPUT)

(OUTPUT)

MIN MAX MIN MAX

t

pd

¶

A or B B or A 1.9 1.85 ns

t

en

S A or B 1 10.7 1 9.5 ns

t

dis

S A or B 1 10.9 1 9.7 ns

¶

The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).

switching characteristics over recommended operating free-air temperature range, CL = 50 pF,
(unless otherwise noted) (see Figure 1)

PARAMETER DESCRIPTION

VCC = 4 V

VCC = 5 V

± 0.5 V

UNIT

MIN MAX MIN MAX

t

mbb

#

Make-before-break time 0 2 0 2 ns

#

The make-before-break time is the time interval between make and break, during the transition from one selected port to the other.

SN74CBT162292
12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS

SCDS052C – MARCH 1998 – REVISED MA Y 1998

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

2.3 V

V

OL

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

7 V

Open

GND

500 Ω

500 Ω

t

PLH

t

PHL

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

t

PZL

t

PZH

t

PLZ

t

PHZ

1.5 V1.5 V

1.5 V 1.5 V

3 V

0 V

1.5 V

1.5 V

V

OH

V

OL

0 V

1.2 V

VOL + 0.3 V

1.2 V

VOH – 0.3 V

Input

3 V

2.3 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Output

t

pd

t

PZL/tPLZ

t

PZH/tPHZ

Open

7 V

Open

TEST S1

0 V

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when connected to the internal 500-Ω

pulldown resistor. W aveform 2 is for an output with internal conditions such that the output is high except when connected to the
internal 500-Ω pulldown resistor.

C. All pulse inputs and DC inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,

tr ≤ 2.5 ns, tf ≤ 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. t

PLZ

and t

PHZ

are the same as t

dis

. Z = R

INT

= 500 Ω.

F. t

PZL

and t

PZH

are the same as ten. Z = R

INT

= 500 Ω.

G. t

PLH

and t

PHL

are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

IMPORTANT NOTICE

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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
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Copyright  1998, Texas Instruments Incorporated