FUNCTION
SN74CBT16214
12-BIT 1-OF-3 FET MULTIPLEXER/DEMULTIPLEXER
SCDS008I – MAY 1993 – REVISED MAY 1998
D
5-Ω Switch Connection Between Two Ports
D
TTL-Compatible Input Levels
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and 300-mil
Shrink Small-Outline (DL) Packages
description
The SN74CBT16214 provides 12 bits of
high-speed TTL-compatible bus switching
between three separate ports. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay.
The device operates as a 12-bit bus-select switch
via the data-select (S0–S2) terminals.
The SN74CBT16214 is characterized for
operation from –40°C to 85°C.
DGG OR DL PACKAGE
(TOP VIEW)
S0
1A
1B3
2A
2B3
3A
3B3
GND
4A
4B3
5A
5B3
6A
6B3
7A
7B3
V
CC
8A
GND
8B3
9A
9B3
10A
10B3
11A
1 1B3
12A
12B3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
S1
S2
1B1
1B2
2B1
2B2
3B1
GND
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
GND
8B2
9B1
9B2
10B1
10B2
1 1B1
1 1B2
12B1
12B2
S2 S1 S0
L L L Z Disconnect
L LH B1 A port = B1 port
L HL B2 A port = B2 port
L HH Z Disconnect
H LL Z Disconnect
H LH B3 A port = B3 port
H HL B1 A port = B1 port
H H H B2 A port = B2 port
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
FUNCTION TABLE
INPUTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
INPUT/OUTPUT
A
Copyright 1998, Texas Instruments Incorporated
1
SN74CBT16214
12-BIT 1-OF-3 FET MULTIPLEXER/DEMULTIPLEXER
SCDS008I – MAY 1993 – REVISED MAY 1998
logic diagram (positive logic)
1A
12A
2
27
54
53
30
29
28
1B1
1B2
3
1B3
12B1
12B2
12B3
1
S0
56
S1
55
S2
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(see Note 2): DGG package 81°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DL package 74°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I
A
§
on
V
0
(INPUT)
(OUTPUT)
SN74CBT16214
12-BIT 1-OF-3 FET MULTIPLEXER/DEMULTIPLEXER
SCDS008I – MAY 1993 – REVISED MAY 1998
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
V
V
T
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
V
I
I
CC
∆I
C
C
r
on
†
All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
‡
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
§
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
Supply voltage 4 5.5 V
CC
High-level control input voltage 2 V
IH
Low-level control input voltage 0.8 V
IL
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
IK
‡
CC
i
io(OFF)
Control inputs VCC = 5.5 V, One input at 3.4 V , Other inputs at VCC or GND 2.5 mA
Control inputs VI = 3 V or 0 4 pF
VCC = 4.5 V, II = –18 mA –1.2 V
VCC = 0, VI = 5.5 V 10
VCC = 5.5 V, VI = 5.5 V or GND ±1
VCC = 5.5 V, IO = 0, VI = VCC or GND 3 µA
VO = 3 V or 0, A = Z 7.5 pF
VCC = 4 V,
TYP at VCC = 4 V
VCC = 4.5 V
, literature number SCBA004.
VI = 2.4 V, II = 15 mA
=
I
VI = 2.4 V, II = 15 mA 6 12
II = 64 mA 4 7
II = 30 mA 4 7
µ
Ω
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
¶
t
pd
t
pd
t
en
t
¶
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
dis
FROM
A or B B or A 0.35 0.25 ns
S B or A 15.3 5.5 13.9 ns
S A or B 16 5.1 14.5 ns
S A or B 12.1 3.6 11.7 ns
TO
VCC = 4 V
MIN MAX MIN MAX
VCC = 5 V
± 0.5 V
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74CBT16214
12-BIT 1-OF-3 FET MULTIPLEXER/DEMULTIPLEXER
SCDS008I – MAY 1993 – REVISED MAY 1998
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
and t
PLZ
PZL
PLH
and t
and t
PHZ
PZH
PHL
500 Ω
500 Ω
1.5 V 1.5 V
are the same as t
are the same as ten.
are the same as tpd.
dis
.
S1
t
PHL
7 V
GND
3 V
0 V
V
V
Open
OH
OL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
t
PLZ
1.5 V
t
PHZ
1.5 V
Open
7 V
Open
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3.5 V
V
OL
V
OH
0 V
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated
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