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SN74CBT16213
24-BIT FET BUS-EXCHANGE SWITCH
SCDS026F – MAY 1995 – REVISED MAY 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
5-Ω Switch Connection Between Two Ports
D
TTL-Compatible Input Levels
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and 300-mil Shrink
Small-Outline (DL) Packages
description
The SN74CBT16213 provides 24 bits of
high-speed TTL-compatible bus switching or
exchanging. The low on-state resistance of the
switch allows connections to be made with
minimal propagation delay.
The device operates as a 24-bit bus switch or a
12-bit bus exchanger that provides data
exchanging between the four signal ports via the
data-select (S0–S2) terminals.
The SN74CBT16213 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
INPUTS/OUTPUTS
L L L Z Z Disconnect
L LH B1 Z A1 port = B1 port
L HL B2 Z A1 port = B2 port
L HH Z B1 A2 port = B1 port
H LL Z B2 A2 port = B2 port
H L H A2 and B2 A1 and B2 A1 port = A2 port = B2 port
H HL B1 B2
A1 port = B1 port
A2 port = B2 port
H H H B2 B1
A1 port = B2 port
A2 port = B1 port
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1998, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
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2
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27
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56
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40
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31
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S0
1A1
1A2
2A1
2A2
3A1
3A2
GND
4A1
4A2
5A1
5A2
6A1
6A2
7A1
7A2
V
CC
8A1
GND
8A2
9A1
9A2
10A1
10A2
1 1A1
1 1A2
12A1
12A2
S1
S2
1B1
1B2
2B1
2B2
3B1
GND
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
GND
8B2
9B1
9B2
10B1
10B2
1 1B1
1 1B2
12B1
12B2
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SN74CBT16213
24-BIT FET BUS-EXCHANGE SWITCH
SCDS026F – MAY 1995 – REVISED MAY 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
S0
S1
S2
12A2
12A1
1A2
1A1
12B2
12B1
1B2
1B1
2
3
27
28
1
56
55
54
53
30
29